Book and thesis
Papers
Feature Vectors Based on Wire Width and Distance for Lithography Hotspot Detection 16 (2023),pp.2-11 (Co-authored) 2023/02/10
Papers
A Proposal of Equivalence Classes for Index Generation Functions Based on Their Row-Shift Decompositions 31st International Workshop on Post-Binary ULSI Systems,pp.9-9 (Co-authored) 2022/05/18
Papers
On a Generation Method of Benchmark Maximally Asymmetric Functions 29th International Workshop on Post-Binary ULSI Systems,pp.36-41 (Co-authored) 2020/11/11
Papers
An Approximate Nearest Neighbor Search Algorithm Using Distance-based Hashing DEXA2018 (The 28th International Conference on Database and Expert Systems Applications) (Lecture Notes in Computer Science) 11030,pp.203-213 (Co-authored) 2018/09/03
Papers
Novel Feature Vectors Considering Distances between Wires for Lithography Hotspot Detection DSD2018 (The 21st Euromicro Digital System Design) 21,pp.85-90 (Co-authored) 2018/08/29
Papers
An FPGA-based Nearest Neighbor Search Engine Using Distance-based Hashing for High-Dimensional Data SASIMI2018 (The 21st Workshop on Synthesis And System Integration of Mixed Information Technology),pp.347-352 (Co-authored) 2018/03/26
Papers
A Programmable Architecture Based on Vectorized EVBDDs for Network Intrusion Detection Using Random Forests NOLTA2017 (The 2017 International Symposium on Nonlinear Theory and Its Applications),pp.132-135 (Co-authored) 2017/12/04
Papers
Table Reference-Based Acceleration of a Lithography Hotspot Detection Method Based on Approximate String Search CENICS2017 (The Tenth International Conference on Advances in Circuits, Electronics and Micro-electronics) 10,pp.8-14 (Co-authored) 2017/09/10
Papers
An Efficient FPGA Implementation of Mahalanobis Distance-Based Outlier Detection for Streaming Data FPT2016 (Field Programmable Technology),pp.257-260 (Co-authored) 2016/12/09
Papers
A High-Speed Programmable Network Intrusion Detection System Based on a Multi-Byte Transition NFA CENICS2016 (The ninth international conference on advances in circuits, Electronics and micro-electronics) Proceedings,pp.45-51 (Co-authored) 2016/07/24
Papers
A Hotspot Detection Method Based on Approximate String Search CENICS2016 (The ninth international conference on advances in circuits, Electronics and micro-electronics) Proceedings,pp.6-12 (Co-authored) 2016/07/24
Papers
Inter-FPGA Routing for Partially Time-Multiplexing Inter-FPGA Signals on Multi-FPGA Systems with Various Topologies IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences,pp.2572-2583 (Co-authored) 2015/12/01
Papers
An Area Efficient Regular Expression Matching Engine Using Partial Reconfiguration for Quick Pattern Updating IPSJ Transactions on System LSI Design Methodology,pp.110-118 (Co-authored) 2014/08
Papers
An ILP-based Optimal Circuit Mapping Method for PLDs Proc. the 21st Reconfigurable Architecture Workshop (in International Parallel and Distributed Processing Symposium Workshops),pp.251-256 (Co-authored) 2014/05
Papers
An NFA-Based Programmable Regular Expression Matching Engine Highly Suitable for FPGA Implementation Proc. the 18th Workshop on Synthesis And System Integration of Mixed Information Technology (SASIMI2013),pp.231-236 (Co-authored) 2013/10/21
Papers
Pattern-Independent Regular Expression Matching Hardware Based on Systolic Algorithm and NFA IEICE Trans. on Information and Systems,pp.2139-2149 (Co-authored) 2013/10/01
Papers
A Flexible and Compact Regular Expression Matching Engine Using Partial Reconfiguration for FPGA Proc. the 2013 Euromicro Conference on Digital System Design (DSD2013),pp.293-296 (Co-authored) 2013/09/04
Papers
A multithreaded Parallel Global Routing Method with Overlapped Routing Regions Proc. the 2013 Euromicro Conference on Digital System Design (DSD2013),pp.591-597 (Co-authored) 2013/09/04
Papers
GPGPU Implementation of Tabu Search for the Quadratic Assignment Problem Proc. Int. Technical Conf. on Circuit/Systems Computers and Communications 2012 (ITC-CSCC2012) (Co-authored) 2012/07/15
Papers
A GPGPU Implementation of Approximate String Matching with Regular Expression Operators and Comparison with Its FPGA Implementation Proc. Int. Conf. Parallel and Distributed Processing Techniques and Applications (PDPTA2012),pp.644-650 (Co-authored) 2012/07
Papers
A Practical FPGA Implementation of Regular Expression Matching with Look-ahead Assertion Proc. Int. Conf. Engineering of Reconfigurable Systems and Algorithms (ERSA2012),pp.105-110 (Co-authored) 2012/07
Papers
A Matching Method for Look-ahead Assertion on Pattern Independent Regular Expression Matching Engine Proc. the 17th Workshop on Synthesis And System Integration of Mixed Information Technology (SASIMI2012),pp.361-366 (Co-authored) 2012/03/09
Papers
Net-based Move in SA-based Placement for a Switch-block-free Reconfigurable Device Proc. the 17th Workshop on Synthesis And System Integration of Mixed Information Technology (SASIMI2012),pp.239-240 (Co-authored) 2012/03/08
Papers
A Physical Design Method for a New Memory-Based Reconfigurable Architecture without Switch Blocks IEICE Trans. on Information and Systems,pp.324-334 (Co-authored) 2012/02
Papers
EDA Environment for Evaluating a New Switch-Block-Free Reconfigurable Architecture Proc. the 2011 Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig2011),pp.448-454 (Co-authored) 2011/11
Papers
An Efficient Hardware Matching Engine for Regular Expression with Nested Kleene Operators Proc. the 21st IEEE Int. Conf. on Field Programabble Logic and applications,pp.157-161 (Co-authored) 2011/09/05
Papers
An Extension of Systolic Regular Expression Matching Hardware for Handling Iteration of Strings Using Quantifiers Proc. Workshop on Synthesis And System Integration of Mixed Information Technologies 2010,pp.412-417 (Co-authored) 2010/10
Papers
Globally Optimal Time-multiplexing of Inter-FPGA Connections for Multi-FPGA Prototyping Systems IPSJ Transaction on System LSI Design Methodology 3,pp.81-90 (Co-authored) 2010/02/15
Papers
Globally Optimal Time-multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Systems Proc. Int. Conf. Field Programmable Logic and Applications 19,pp.212-217 (Co-authored) 2009/08
Papers
A Parallel Simulated Annealing for LSI Floorplanning Running on Multi-core Processors Proc. Int. Technical Conf. on Circuit/Systems Computers and Communications 2009 24,pp.851-854 (Co-authored) 2009/07
Papers
Design and FPGA Implementation of Efficient Discrete Function Generators Using Piecewise Polynomial Approximations Proc. Int. Technical Conf. on Circuit/Systems Computers and Communications 2009 24,pp.1016-1019 (Co-authored) 2009/07
Papers
Evaluation of Introducing Multiple Time-multiplexing Degrees to Inter-FPGA Connections on Multi-FPGA Systems Proc. Int. Technical Conf. on Circuit/Systems Computers and Communications 2009 24,pp.1032-1035 (Co-authored) 2009/07
Papers
Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems IEICE Transactions on Fundamentals E91-A (12),pp.3539-3547 (Co-authored) 2008/12
Papers
ILP-based Optimization of Time-multiplexed I/O Assignment for Multi-FPGA Systems Proceedings of IEEE International Symposium on Circuit and Systems 2008,pp.1800-1803 (Co-authored) 2008/05
Papers
A Performance-driven Bipartitioning Method for Multi-FPGA Implementation with Time-multiplexed I/Os IEICE Transactions on Fundamentals,pp.924-931 (Co-authored) 2007/05
Papers
A Performance-driven Circuit Bipartitioning Algorithm for Multi-FPGA Implementation with Time-multiplexed I/Os Proc. Int. Conf. on Field Programmable Technology 2006,pp.361-364 (Co-authored) 2006/12
Papers
Network-Flow Based Delay Aware Partitioning Algorithm Proceedings of the 13th Workshop on Synthesis and System Integration of Mixed Information technologies,pp.417-422 (Co-authored) 2006/04
Papers
An Improvement of Network-Flow Based Multi-Way Circuit Partitioning Algorithm IEICE Transactions on Fundamentals,pp.655-663 (Co-authored) 2002/03