Book and thesis
Books
Broadside transition test generation for partial scan circuits through stuck-at test generation (Co-authored) 2007
Papers
A Design of Fully Stochastic Computing Neurons Focused on the Gain of Sigmoid Functions,pp.552-561 (Co-authored) 2021/07
Papers
Transient Fault Tolerant State Assignment for Stochastic Computing Based on Linear Finite State Machines IEICE Trans. Fundamentals E103-A (12),pp.1464-1471 (Co-authored) 2020/12
Papers
State encoding with stochastic numbers for transient fault tolerant linear finite state machines Proc. 32nd IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT '19),pp.1-6 (Co-authored) 2019/10
Papers
An empirical approach to RTL scan path design focusing on structural interpretation in logic synthesis Proc. 3rd IEEE International Test Conference in Asia (ITC-Asia '19),pp.55-60 (Co-authored) 2019/09
Papers
Effective utilization of register-transfer paths based on enhancing multiplexer functions in RTL scan design Digest of Papers 19th IEEE Workshop on RTL and High Level Testing (WRTLT '18),pp.1-6 (Co-authored) 2018/10
Papers
Experimental evaluation of test cost reduction by scan chain testing in RTL scan circuits Digest of Papers 18th IEEE Workshop on RTL and High Level Testing (WRTLT '17),pp.1-6 (Co-authored) 2017/11
Papers
State assignment for fault tolerant stochastic computing with linear finite state machines Proc. 1st International Test Conference in Asia (ITC-Asia '17),pp.156-161 (Co-authored) 2017/09
Papers
Exploration of four-phase dual-rail asynchronous RTL design for delay-robustness Digest of Papers 17th IEEE Workshop on RTL and High Level Testing (WRTLT '16),pp.1-6 (Co-authored) 2016/11
Papers
Impact of state assignment on error resilient stochastic computing with linear finite state machines Digest of Papers 17th IEEE Workshop on RTL and High Level Testing (WRTLT '16),pp.1-6 (Co-authored) 2016/11
Papers
Stochastic number generation with internal signals of logic circuits Proc. 20th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI '16),pp.1-2 (Co-authored) 2016/10
Papers
Compact and accurate digital filters based on stochastic computing IEEE Trans. on Emerging Topics in Computing (Co-authored) 2016/09
Papers
A prototype of a hardware SAT solver for similar large instances and its application to test generation Digest of Papers 16th IEEE Workshop on RTL and High Level Testing (WRTLT '15),pp.1-5 (Co-authored) 2015/11
Papers
Logic simplification by minterm complement for error tolerant application Proc. IEEE International Conference on Computer Design (ICCD '15),pp.94-100 (Co-authored) 2015/10
Papers
A practical approach for logic simplification based on fault acceptability for error tolerant application Proc. 20th IEEE European Test Symposium (ETS '15),pp.1-2 (Co-authored) 2015/05
Papers
Designing area-efficient controllers for multi-cycle transient fault tolerant systems Proc. 20th IEEE European Test Symposium (ETS '15),pp.1-2 (Co-authored) 2015/05
Papers
A controller design in high-level synthesis for long duration transient fault tolerance Digest of Papers 15th IEEE Workshop on RTL and High Level Testing (WRTLT '14) (Co-authored) 2014/11
Papers
A scheduling algorithm in datapath synthesis for long duration transient fault tolerance Proc. 27th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT '14),pp.128-133 (Co-authored) 2014/10
Papers
Compact and accurate stochastic circuits with shared random number sources Proc. IEEE International Conference on Computer Design (ICCD '14),pp.361-366 (Co-authored) 2014/10
Papers
A design of error correctable response analyzers for reliable built-in self-test Digest of Papers 14th IEEE Workshop on RTL and High Level Testing (WRTLT '13) (Co-authored) 2013/11
Papers
A heuristic algorithm for operational unit binding to synthesize multi-cycle transient fault tolerant datapaths Digest of Papers 14th IEEE Workshop on RTL and High Level Testing (WRTLT '13) (Co-authored) 2013/11
Papers
A transient fault tolerant test pattern generator for on-line built-in self-test Proc. 22nd IEEE Asian Test Symp (ATS '13) (Co-authored) 2013/11
Papers
Utilizing register transfer level false paths for circuit optimization with a logic synthesis tool Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS '12) (Co-authored) 2012/12
Papers
A study on error correctable test pattern generator for reliable built-in self test Proc. 13th IEEE Workshop on RTL and High Level Testing (WRTLT '12) (Co-authored) 2012/11
Papers
Exact and heuristic methods of generating compact tests for hold-time violations Proc. 13th IEEE Workshop on RTL and High Level Testing (WRTLT '12) (Co-authored) 2012/11
Papers
Modeling economics of LSI design and manufacturing for test design selection Proc. IEEE International Conference on Computer Design (ICCD '12) (Co-authored) 2012/10
Papers
A technique for SAT-based test generation through history of reusing solutions 17th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI '12) (Co-authored) 2012/03
Papers
Flexible test scheduling for an asynchronous on-chip interconnect through special data transfer IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences E94-A (12),pp.2563-2570 (Co-authored) 2011/12
Papers
An approach to hardware SAT solvers for test generation based on instance similarity 12th IEEE Workshop on RTL and High Level Testing (WRTLT '11) (Co-authored) 2011/11
Papers
Power-constrained test generation for hold-time faults using integer linear programming 4th IEEE International Workshop on Impact of Low-Power Design on Test and Reliability (LPonTR '11) (Co-authored) 2011/05
Papers
Backward-data-direction clocking and relevant optimal register assignment in datapath synthesis IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences E94-A (4),pp.1067-1081 (Co-authored) 2011/04
Papers
Indirect detection of clock skew induced hold-time violations on functional paths using scan shift operations 14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS '11) (Co-authored) 2011/04
Papers
An approach to test scheduling for asynchronous on-chip interconnects using integer programming Digest of Papers 11th IEEE Workshop on RTL and High Level Testing (WRTLT '10) (Co-authored) 2010/12
Papers
Test scheduling algorithms for delay-insensitive chip area interconnects based on cone partitioning Proc. 3rd International Workshop on the Impact of Low-Power Design on Test and Reliability (LPonTR '10) (Co-authored) 2010/05
Papers
A pseudo-boolean technique for generating compact transition tests with all-output-propagation properties Proc. IEEE International Symposium on Electronic Design, Test and Applications (DELTA '10),pp.293-196 (Co-authored) 2010/01
Papers
Safe clocking for the setup and hold timing constraints in datapath synthesis Proc. 19th ACM Great Lakes symposium on VLSI (GLSVLSI '09),pp.27-32 (Co-authored) 2009/05
Papers
Optimal register assignment with minimum-path delay compensation for variation-aware datapaths IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences E92-A (4),pp.1096-1105 (Co-authored) 2009/04
Papers
A conjecture on the number of extra registers in safe clocking-based register assignment Proc. 15th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI '09),pp.131-136 (Co-authored) 2009/03
Papers
On the derivation of a minimum test set in high quality transition testing Proc. IEEE Latin-American Test Workshop (LATW '09),pp.1-6 (Co-authored) 2009/03
Papers
Safe clocking register assignment in datapath synthesis Proc. IEEE International Conference on Computer Design (ICCD '08),pp.120-127 (Co-authored) 2008/10
Papers
Minimizing minimum delay compensations for timing variation-aware datapath synthesis Proc. IEEE Mid-West Symposium on Circuits and Systems (MWSCAS '08),pp.97-100 (Co-authored) 2008/08
Papers
Novel register sharing in datapath for structural robustness against delay variation IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences E91-A (4),pp.1044-1053 (Co-authored) 2008/04
Papers
Generation of power-constrained scan tests and its difficulty Proc. IEEE International Design and Test Workshop (IDT '07),pp.71-76 (Co-authored) 2007/12
Papers
Efficient path delay test generation based on stuck-at test generation using checker circuitry Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD '07),pp.418-423 (Co-authored) 2007/11
Papers
Structural robustness of datapaths against delay-variations Proc. 14th Workshop on Synthesis and System Integration of Mixed Information Technology (SASIMI '07),pp.272-279 (Co-authored) 2007/10
Papers
A new test generation model for broadside transition testing of partial scan circuits Proc. 14th IFIP/IEEE/ACM International Conference on Very Large Scale Integration (VLSI-SoC '06),pp.308-313 (Co-authored) 2006/10
Papers
A low power deterministic test using scan chain disable technique IEICE Trans. on Information and Systems E89-D (6),pp.1931-1939 (Co-authored) 2006/06
Papers
Efficient constraint extraction for template-based processor self-test generation Proc. 14th IEEE Asian Test Symposium (ATS '05),pp.444-447 (Co-authored) 2005/12
Papers
A low power deterministic test using scan chain disable technique Digest of Papers 6th IEEE Workshop on RTL and High Level Testing (WRTLT '05),pp.184-191 (Co-authored) 2005/07
Papers
Acceleration of transition test generation for acyclic sequential circuits utilizing constrained combinational stuck-at test generation Proc. 10th IEEE European Test Symposium (ETS '05),pp.48-53 (Co-authored) 2005/05
Papers
A design scheme for delay testing of controllers using state transition information IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences (Special Section on VLSI Design and CAD Algorithms) E87-A (12),pp.3200-3207 (Co-authored) 2004/12
Papers
A design methodology to realize delay testable controllers using state transition information Proc. 9th IEEE European Test Symposium (ETS '04),pp.168-173 (Co-authored) 2004/05
Papers
A method of design for delay fault testability of controllers IEICE Technical Report (DC2003-38) 103 (476),pp.25-30 (Co-authored) 2003/11
Papers
An approach to non-scan design for delay fault testability of controllers Digest of Papers 4th IEEE Workshop on RTL and High Level Testing (WRTLT '03),pp.79-85 (Co-authored) 2003/11
Papers
Reducibility of sequential test generation to combinational test generation for several delay fault models Proc. 12th IEEE Asian Test Symposium (ATS '03),pp.58-63 (Co-authored) 2003/11
Papers
A path delay test generation method for sequential circuits based on reducibility to combinational test generation Digest of Papers 8th IEEE European Test Workshop (ETW '03),pp.307-312 (Co-authored) 2003/05