教員総覧 - 岩垣　剛 | 広島市立大学

イワガキ　ツヨシ Iwagaki Tsuyoshi
岩垣　剛

所属広島市立大学大学院情報科学研究科情報工学専攻

広島市立大学情報科学部情報工学科

職種助教

著書・論文歴
著書	Broadside transition test generation for partial scan circuits through stuck-at test generation (共著) 2007
論文	シグモイド関数のゲインに着目した完全ストカスティック計算ニューロンの設計電子情報通信学会論文誌 D J104-D (7),552-561頁 (共著) 2021/07
論文	Transient Fault Tolerant State Assignment for Stochastic Computing Based on Linear Finite State Machines IEICE Trans. Fundamentals E103-A (12),1464-1471頁 (共著) 2020/12
論文	State encoding with stochastic numbers for transient fault tolerant linear finite state machines Proc. 32nd IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT '19),1-6頁 (共著) 2019/10
論文	An empirical approach to RTL scan path design focusing on structural interpretation in logic synthesis Proc. 3rd IEEE International Test Conference in Asia (ITC-Asia '19),55-60頁 (共著) 2019/09
論文	Effective utilization of register-transfer paths based on enhancing multiplexer functions in RTL scan design Digest of Papers 19th IEEE Workshop on RTL and High Level Testing (WRTLT '18),1-6頁 (共著) 2018/10
論文	Experimental evaluation of test cost reduction by scan chain testing in RTL scan circuits Digest of Papers 18th IEEE Workshop on RTL and High Level Testing (WRTLT '17),1-6頁 (共著) 2017/11
論文	State assignment for fault tolerant stochastic computing with linear finite state machines Proc. 1st International Test Conference in Asia (ITC-Asia '17),156-161頁 (共著) 2017/09
論文	Exploration of four-phase dual-rail asynchronous RTL design for delay-robustness Digest of Papers 17th IEEE Workshop on RTL and High Level Testing (WRTLT '16),1-6頁 (共著) 2016/11
論文	Impact of state assignment on error resilient stochastic computing with linear finite state machines Digest of Papers 17th IEEE Workshop on RTL and High Level Testing (WRTLT '16),1-6頁 (共著) 2016/11
論文	Stochastic number generation with internal signals of logic circuits Proc. 20th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI '16),1-2頁 (共著) 2016/10
論文	Compact and accurate digital filters based on stochastic computing IEEE Trans. on Emerging Topics in Computing (共著) 2016/09
論文	A prototype of a hardware SAT solver for similar large instances and its application to test generation Digest of Papers 16th IEEE Workshop on RTL and High Level Testing (WRTLT '15),1-5頁 (共著) 2015/11
論文	Logic simplification by minterm complement for error tolerant application Proc. IEEE International Conference on Computer Design (ICCD '15),94-100頁 (共著) 2015/10
論文	A practical approach for logic simplification based on fault acceptability for error tolerant application Proc. 20th IEEE European Test Symposium (ETS '15),1-2頁 (共著) 2015/05
論文	Designing area-efficient controllers for multi-cycle transient fault tolerant systems Proc. 20th IEEE European Test Symposium (ETS '15),1-2頁 (共著) 2015/05
論文	A controller design in high-level synthesis for long duration transient fault tolerance Digest of Papers 15th IEEE Workshop on RTL and High Level Testing (WRTLT '14) (共著) 2014/11
論文	A scheduling algorithm in datapath synthesis for long duration transient fault tolerance Proc. 27th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT '14),128-133頁 (共著) 2014/10
論文	Compact and accurate stochastic circuits with shared random number sources Proc. IEEE International Conference on Computer Design (ICCD '14),361-366頁 (共著) 2014/10
論文	A design of error correctable response analyzers for reliable built-in self-test Digest of Papers 14th IEEE Workshop on RTL and High Level Testing (WRTLT '13) (共著) 2013/11
論文	A heuristic algorithm for operational unit binding to synthesize multi-cycle transient fault tolerant datapaths Digest of Papers 14th IEEE Workshop on RTL and High Level Testing (WRTLT '13) (共著) 2013/11
論文	A transient fault tolerant test pattern generator for on-line built-in self-test Proc. 22nd IEEE Asian Test Symp (ATS '13) (共著) 2013/11
論文	Utilizing register transfer level false paths for circuit optimization with a logic synthesis tool Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS '12) (共著) 2012/12
論文	A study on error correctable test pattern generator for reliable built-in self test Proc. 13th IEEE Workshop on RTL and High Level Testing (WRTLT '12) (共著) 2012/11
論文	Exact and heuristic methods of generating compact tests for hold-time violations Proc. 13th IEEE Workshop on RTL and High Level Testing (WRTLT '12) (共著) 2012/11
論文	Modeling economics of LSI design and manufacturing for test design selection Proc. IEEE International Conference on Computer Design (ICCD '12) (共著) 2012/10
論文	A technique for SAT-based test generation through history of reusing solutions 17th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI '12) (共著) 2012/03
論文	Flexible test scheduling for an asynchronous on-chip interconnect through special data transfer IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences E94-A (12),2563-2570頁 (共著) 2011/12
論文	An approach to hardware SAT solvers for test generation based on instance similarity 12th IEEE Workshop on RTL and High Level Testing (WRTLT '11) (共著) 2011/11
論文	Power-constrained test generation for hold-time faults using integer linear programming 4th IEEE International Workshop on Impact of Low-Power Design on Test and Reliability (LPonTR '11) (共著) 2011/05
論文	Backward-data-direction clocking and relevant optimal register assignment in datapath synthesis IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences E94-A (4),1067-1081頁 (共著) 2011/04
論文	Indirect detection of clock skew induced hold-time violations on functional paths using scan shift operations 14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS '11) (共著) 2011/04
論文	An approach to test scheduling for asynchronous on-chip interconnects using integer programming Digest of Papers 11th IEEE Workshop on RTL and High Level Testing (WRTLT '10) (共著) 2010/12
論文	Test scheduling algorithms for delay-insensitive chip area interconnects based on cone partitioning Proc. 3rd International Workshop on the Impact of Low-Power Design on Test and Reliability (LPonTR '10) (共著) 2010/05
論文	A pseudo-boolean technique for generating compact transition tests with all-output-propagation properties Proc. IEEE International Symposium on Electronic Design, Test and Applications (DELTA '10),293-196頁 (共著) 2010/01
論文	Safe clocking for the setup and hold timing constraints in datapath synthesis Proc. 19th ACM Great Lakes symposium on VLSI (GLSVLSI '09),27-32頁 (共著) 2009/05
論文	Optimal register assignment with minimum-path delay compensation for variation-aware datapaths IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences E92-A (4),1096-1105頁 (共著) 2009/04
論文	A conjecture on the number of extra registers in safe clocking-based register assignment Proc. 15th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI '09),131-136頁 (共著) 2009/03
論文	On the derivation of a minimum test set in high quality transition testing Proc. IEEE Latin-American Test Workshop (LATW '09),1-6頁 (共著) 2009/03
論文	Safe clocking register assignment in datapath synthesis Proc. IEEE International Conference on Computer Design (ICCD '08),120-127頁 (共著) 2008/10
論文	Minimizing minimum delay compensations for timing variation-aware datapath synthesis Proc. IEEE Mid-West Symposium on Circuits and Systems (MWSCAS '08),97-100頁 (共著) 2008/08
論文	Novel register sharing in datapath for structural robustness against delay variation IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences E91-A (4),1044-1053頁 (共著) 2008/04
論文	Generation of power-constrained scan tests and its difficulty Proc. IEEE International Design and Test Workshop (IDT '07),71-76頁 (共著) 2007/12
論文	Efficient path delay test generation based on stuck-at test generation using checker circuitry Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD '07),418-423頁 (共著) 2007/11
論文	Structural robustness of datapaths against delay-variations Proc. 14th Workshop on Synthesis and System Integration of Mixed Information Technology (SASIMI '07),272-279頁 (共著) 2007/10
論文	A new test generation model for broadside transition testing of partial scan circuits Proc. 14th IFIP/IEEE/ACM International Conference on Very Large Scale Integration (VLSI-SoC '06),308-313頁 (共著) 2006/10
論文	A low power deterministic test using scan chain disable technique IEICE Trans. on Information and Systems E89-D (6),1931-1939頁 (共著) 2006/06
論文	Efficient constraint extraction for template-based processor self-test generation Proc. 14th IEEE Asian Test Symposium (ATS '05),444-447頁 (共著) 2005/12
論文	A low power deterministic test using scan chain disable technique Digest of Papers 6th IEEE Workshop on RTL and High Level Testing (WRTLT '05),184-191頁 (共著) 2005/07
論文	Acceleration of transition test generation for acyclic sequential circuits utilizing constrained combinational stuck-at test generation Proc. 10th IEEE European Test Symposium (ETS '05),48-53頁 (共著) 2005/05
論文	A design scheme for delay testing of controllers using state transition information IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences (Special Section on VLSI Design and CAD Algorithms) E87-A (12),3200-3207頁 (共著) 2004/12
論文	A design methodology to realize delay testable controllers using state transition information Proc. 9th IEEE European Test Symposium (ETS '04),168-173頁 (共著) 2004/05
論文	不連続再収斂順序回路の遅延故障に対するテスト生成法 J86-D-I (12),872-883頁 (共著) 2003/12
論文	A method of design for delay fault testability of controllers IEICE Technical Report (DC2003-38) 103 (476),25-30頁 (共著) 2003/11
論文	An approach to non-scan design for delay fault testability of controllers Digest of Papers 4th IEEE Workshop on RTL and High Level Testing (WRTLT '03),79-85頁 (共著) 2003/11
論文	Reducibility of sequential test generation to combinational test generation for several delay fault models Proc. 12th IEEE Asian Test Symposium (ATS '03),58-63頁 (共著) 2003/11
論文	A path delay test generation method for sequential circuits based on reducibility to combinational test generation Digest of Papers 8th IEEE European Test Workshop (ETW '03),307-312頁 (共著) 2003/05
論文	不連続再収斂構造に基づくパス遅延故障に対する部分拡張スキャン設計法信学技報 (FTS2001-84) 101 (658),53-60頁 (共著) 2002/02