Faculty Information - Nagayama Shinobu |

Nagayama Shinobu

Department / Course Hiroshima City University Graduate School Graduate School of Information Sciences Major in Computer and Network Engineering

Hiroshima City University Faculty of Information Sciences Department of Computer and Network Engineering

Job Professor

Book and thesis
Papers	A Proposal of Invariant Operations on Maximally Asymmetric Functions for Their Efficient Generation Journal of Multiple-Valued Logic and Soft Computing (Co-authored) 2025/06/01
Papers	Functional Decomposition of Symmetric Multiple-Valued Functions and Their Compact Representation in Decision Diagrams IEICE Transactions on Information and Systems E107-D (8),pp.922-929 (Co-authored) 2024/08/01
Papers	On Representation of Maximally Asymmetric Functions Based on Decision Diagrams Journal of Applied Logics 10 (6),pp.1105-1130 (Co-authored) 2023/12/01
Papers	Feature Vectors Based on Wire Width and Distance for Lithography Hotspot Detection IPSJ Transactions on System LSI Design Methodology 16,pp.2-11 (Co-authored) 2023/02/01
Papers	A Fast Method for Exactly Optimum Linear Decomposition of Index Generation Functions Journal of Multiple-Valued Logic and Soft Computing 38 (3-4),pp.387-405 (Co-authored) 2022/06/01
Papers	An exact optimization method using ZDDs for linear decomposition of symmetric index generation functions International Federation of Computational Logic Journal of Logic and Their Applications 5 (9),pp.1849-1866 (Co-authored) 2018/12/01
Papers	A balanced decision tree based heuristic for linear decomposition of index generation functions IEICE Transactions on Information and Systems E100-D (8),pp.1583-1591 (Co-authored) 2017/08/01
Papers	多状態システムの高速な解析のための枝重みつきMDDの最適化について IEICE Transactions on Information and Systems E97-D (9),pp.2234-2242 (Co-authored) 2014/09/01
Papers	An Area Efficient Regular Expression Matching Engine Using Partial Reconfiguration for Quick Pattern Updating IPSJ Transactions on System LSI Design Methodology (7),pp.110-118 (Co-authored) 2014/08/04
Papers	初等関数の区分的算術式と数値計算回路の設計への応用 Journal of Multiple-Valued Logic and Soft Computing 23 (3-4),pp.293-313 (Co-authored) 2014/06/01
Papers	Simple Hybrid Scaling-Free CORDIC Solution for FPGAs International Journal of Reconfigurable Computing 2014,pp.4pages (Co-authored) 2014/04/25
Papers	EVMDDに基づく多状態システムの解析法と診断法 Journal of Multiple-Valued Logic and Soft Computing 22 (1-2),pp.59-78 (Co-authored) 2014/02/01
Papers	Pattern-Independent Regular Expression Matching Hardware Based on Systolic Algorithm and NFA IEICE Transactions on Information and Systems,pp.2139-2149 (Co-authored) 2013/10/01
Papers	A Systolic Algorithm for Approximate Regular Expression Matching and Its FPGA Implementation IEICE Transactions on Information and Systems,pp.935-944 (Co-authored) 2011/06/01
Papers	多値決定グラフを用いた二変数数学関数回路のシステマチックな設計法 IEICE Transactions on Information and Systems E93-D (8),pp.2059-2067 (Co-authored) 2010/08/01
Papers	Programmable architectures and design methods for two-variable numeric function generators IPSJ Transactions on System LSI Design Methodology 3 (0),pp.118-129 (Co-authored) 2010/02/01
Papers	A Pattern Independent Regular Expression String Matching Machine and Its FPGA Implementation IEICE Transactions on Information and Systems,pp.2159-2167 (Co-authored) 2009/12/01
Papers	初等関数のグラフ表現の複雑さ IEEE Transactions on Computers 58 (1),pp.106-119 (Co-authored) 2009/01/01
Papers	再帰的分割法とEVBDDを用いた数値計算回路の設計法 IEICE Transactions on Fundamentals of Electronics E90-A (12),pp.2752-2761 (Co-authored) 2007/12/01
Papers	LUTカスケードを用いた数値計算回路 IEEE Transactions on Computers 56 (6),pp.826-838 (Co-authored) 2007/06/01
Papers	二次近似法に基づくコンパクトな数値計算回路の構成とその合成法 IEICE Transactions on Fundamentals of Electronics E89-A (12),pp.3510-3518 (Co-authored) 2006/12/01
Papers	ヘテロジニアスMDDの最適化について IEEE Transactions on CAD 24 (11),pp.1645-1659 (Co-authored) 2005/11/01
Papers	決定グラフにおける平均パス長の最小化アルゴリズムと発見的手法 Journal of Multiple-Valued Logic and Soft Computing 11 (5-6),pp.437-465 (Co-authored) 2005/08/01
Papers	LUTリングによる多出力関数の実現 IEICE Transactions on Fundamentals of Electronics E87-A (12),pp.3141-3150 (Co-authored) 2004/12/01
Papers	多値決定グラフの面積時間複雑度 IEICE Transactions on Fundamentals of Electronics E87-A (5),pp.1020-1028 (Co-authored) 2004/05/01
Papers	ヘテロジニアスMDDを用いた論理関数のコンパクトな表現法 IEICE Transactions on Fundamentals of Electronics E86-A (12),pp.3168-3175 (Co-authored) 2003/12/01
Books	Fast Network Intrusion Detection Systems (Co-authored) 2016/05/01
Books	Applications of Zero-Suppressed Decision Diagrams (Co-authored) 2014/11/01
Books	Research for Development of Flexible Dedicated Circuits (Sole-authored) 2011/08/01
Papers	Ternary Function Classification Using Machine Learning IEEE International Symposium on Multiple-Valued Logic,pp.65-70 (Co-authored) 2024/05/29
Papers	A Proposal of Equivalence Classes in Maximally Asymmetric Functions and Their Application to Benchmark Generation IEEE International Symposium on Multiple-Valued Logic,pp.65-70 (Co-authored) 2024/05/29
Papers	対称関数の Sensitivity による列挙 Reed-Muller 2023 Workshop (Co-authored) 2023/05/24
Papers	対称多値関数の関数分解に基づく表現法 IEEE International Symposium on Multiple-Valued Logic (Co-authored) 2023/05/22
Papers	多値決定木を用いたハイパースペクトル画像内の異常検出に関する実験的評価 32nd International Workshop on Post-Binary ULSI Systems,pp.8-8 (Co-authored) 2023/05/21
Papers	最大非対称関数の決定グラフについて IEEE International Symposium on Multiple-Valued Logic,pp.164-169 (Co-authored) 2022/05/21
Papers	行シフト分解に基づくインデックス生成関数の同値類の一提案 31st International Workshop on Post-Binary ULSI Systems,pp.9-9 (Co-authored) 2022/05/18
Papers	インデックス生成関数の発見的線形分解法の解の質向上 IEEE International Symposium on Multiple-Valued Logic,pp.13-18 (Co-authored) 2021/05/25
Papers	最大非対称関数のベンチマーク生成法について 29th International Workshop on Post-Binary ULSI Systems,pp.36-41 (Co-authored) 2020/11/11
Papers	対称インデックス生成関数の最適な線形分解について IEEE International Symposium on Multiple-Valued Logic,pp.130-136 (Co-authored) 2020/05/20
Papers	多値分割関数の性質 IEEE International Symposium on Multiple-Valued Logic,pp.82-87 (Co-authored) 2020/05/20
Papers	インデックス生成関数の最適な線形分解のための動的計画法 IEEE International Symposium on Multiple-Valued Logic,pp.144-149 (Co-authored) 2019/05/21
Papers	A Nearest Neighbor Search Engine Using Distance-based Hashing International Conference on Field Programmable Technology,pp.153-160 (Co-authored) 2018/12/13
Papers	An Approximate Nearest Neighbor Search Algorithm Using Distance-based Hashing International Conference on Database and Expert Systems Applications,pp.203-213 (Co-authored) 2018/09/03
Papers	Novel Feature Vectors Considering Distances between Wires for Lithography Hotspot Detection EUROMICRO Conference on Digital System Design Architectures, Methods, and Tools,pp.85-90 (Co-authored) 2018/08/29
Papers	ZDDを用いたインデックス生成関数の線形分解のための厳密最適化手法 IEEE International Symposium on Multiple-Valued Logic,pp.144-149 (Co-authored) 2018/05/17
Papers	An FPGA-based Nearest Neighbor Search Engine Using Distance-Based Hashing for High-Dimensional Data Workshop on Synthesis And System Integration of Mixed Information technologies,pp.347-352 (Co-authored) 2018/03/27
Papers	ランダムフォレストを用いたネットワーク不正侵入検知のためのベクトル化EVBDDに基づくプログラマブルアーキテクチャ International Symposium on Nonlinear Theory and Its Applications,pp.132-135 (Co-authored) 2017/12/06
Papers	Table Reference-Based Acceleration of a Lithography Hotspot Detection Method Based on Approximate String Search International Conference on Advances in Circuits, Electronics and Micro-electronics,pp.8-14 (Co-authored) 2017/09/10
Papers	インデックス生成関数の線形分解のための厳密最適化アルゴリズム IEEE International Symposium on Multiple-Valued Logic,pp.161-166 (Co-authored) 2017/05/23
Papers	An efficient FPGA implementation of Mahalanobis distance-based outlier detection for streaming data International Conference on Field Programmable Technology,pp.253-256 (Co-authored) 2016/12/09
Papers	多バイト遷移NFAに基づく高速かつ書換え可能なネットワーク侵入検知システム International Conference on Advances in Circuits, Electronics and Micro-electronics,pp.45-51 (Co-authored) 2016/07/29
Papers	近似文字列探索に基づくホットスポット検出手法 International Conference on Advances in Circuits, Electronics and Micro-electronics,pp.6-12 (Co-authored) 2016/07/25
Papers	インデックス生成関数の線形分解のための効率的な発見的手法 IEEE International Symposium on Multiple-Valued Logic,pp.96-101 (Co-authored) 2016/05/20
Papers	An Improved Methodology for System Threat Analysis Using Multiple-Valued Logic and Conditional Probabilities The SDPS 20th International Conference on Transformative Science & Engineering, Business and Social Innovation,pp.1-5 (Co-authored) 2015/11/01
Papers	多状態システムの解析の高速化のためのEVMDDの枝削減 IEEE International Symposium on Multiple-Valued Logic,pp.170-175 (Co-authored) 2015/05/20
Papers	On Regular Expression Matching Methods for Fast Network Intrusion Detection Systems with High Maintainability 11th International Workshop on Boolean Problems (IWSBP 2014),pp.171-188 (Co-authored) 2014/09/19
Papers	Fast Regular Expression Matching Based On Dual Glushkov NFA The Prague Stringology Conference 2014,pp.3-16 (Co-authored) 2014/09/01
Papers	An ILP-based Optimal Circuit Mapping Method for PLDs IEEE 28th International Parallel & Distributed Processing Symposium Workshops,pp.251-256 (Co-authored) 2014/05/20
Papers	System Probability Distribution Modeling using MDDs IEEE International Symposium on Multiple-Valued Logic,pp.196-201 (Co-authored) 2014/05/19
Papers	部分的に依存関係のある部品を持つ多状態システムの多値決定グラフを用いた解析法 IEEE International Symposium on Multiple-Valued Logic,pp.190-195 (Co-authored) 2014/05/19
Papers	An NFA-based programmable regular expression matching engine highly suitable for FPGA implementation Workshop on Synthesis And System Integration of Mixed Information technologies,pp.231-236 (Co-authored) 2013/10/22
Papers	重複配線領域を許したマルチスレッド並列グローバル配線手法 EUROMICRO Conference on Digital System Design Architectures, Methods, and Tools,pp.591-597 (Co-authored) 2013/09/05
Papers	FPGAの部分再構成を用いた柔軟かつコンパクトな正規表現マッチングエンジン EUROMICRO Conference on Digital System Design Architectures, Methods, and Tools,pp.293-296 (Co-authored) 2013/09/04
Papers	ZBDDを用いた効率的な正規表現マッチング手法 Reed-Muller Workshop 2013,pp.48-54 (Sole-authored) 2013/05/25
Papers	多状態システムの高速な解析のための変数グループ化によるEVMDDの枝数最小化手法 IEEE International Symposium on Multiple-Valued Logic,pp.284-289 (Co-authored) 2013/05/24
Papers	A GPGPU Implementation of Approximate String Matching with Regular Expression Operators and Comparison with Its FPGA Implementation International Conference on Parallel & Distributed Processing Techniques & Applications,pp.644-650 (Co-authored) 2012/07/17
Papers	GPGPU implementation of tabu search for the quadratic assignment problem The 27th International Technical Conference on Circuits/Systems, Computers and Communications,pp.F-M2-06 (Co-authored) 2012/07/16
Papers	EVMDDを用いた多状態システムの解析 IEEE International Symposium on Multiple-Valued Logic,pp.122-127 (Co-authored) 2012/05/14
Papers	A Matching Method for Look-ahead Assertion on Pattern Independent Regular Expression Matching Engine Workshop on Synthesis And System Integration of Mixed Information technologies,pp.361-366 (Co-authored) 2012/03/09
Papers	An efficient hardware matching engine for regular expression with nested kleene operators International Conference on Field Programmable Logic and Applications,pp.157-161 (Co-authored) 2011/09/05
Papers	スプライン補間とバイリニア補間を用いた書換え可能な2変数離散関数の設計法 EUROMICRO Conference on Digital System Design Architectures, Methods, and Tools,pp.701-707 (Co-authored) 2011/09/01
Papers	区分的算術式に基づく数学関数回路 IEEE International Symposium on Multiple-Valued Logic,pp.16-21 (Co-authored) 2011/05/23
Papers	An FPGA-based text search engine for approximate regular expression matching International Conference on Field Programmable Technology,pp.184-191 (Co-authored) 2010/12/09
Papers	An extension of systolic regular expression matching hardware for handling iteration of strings using quantifiers Workshop on Synthesis And System Integration of Mixed Information technologies,pp.412-417 (Co-authored) 2010/10/19
Papers	区分的EVMDDに基づく浮動小数点数学関数回路 IEEE International Symposium on Multiple-Valued Logic,pp.223-228 (Co-authored) 2010/05/27
Papers	A systolic string matching algorithm for high-speed recognition of a restricted regular set International Conference on Engineering of Reconfigurable Systems and Algorithms,pp.151-157 (Co-authored) 2009/07/13
Papers	A parallel simulated annealing algorithm for LSI floorplanning running on multicore processors The 24th International Technical Conference on Circuits/Systems, Computers and Communications,pp.851-854 (Co-authored) 2009/07/05
Papers	Design and FPGA implementation of efficient discrete function generators using piecewise polynomial The 24th International Technical Conference on Circuits/Systems, Computers and Communications,pp.1016-1019 (Co-authored) 2009/07/05
Papers	EVMDDを用いた単調初等関数の浮動小数点回路 IEEE International Symposium on Multiple-Valued Logic,pp.349-355 (Co-authored) 2009/05/21
Papers	離散関数のための決定グラフを用いた数値計算回路 18th International Workshop on Post-Binary ULSI Systems,pp.36-41 (Co-authored) 2009/05/20
Papers	A fast regular expression matching engine for an FPGA-based network intrusion detection system Workshop on Synthesis And System Integration of Mixed Information technologies,pp.88-93 (Co-authored) 2009/03/09
Papers	シストリック正規表現パターンマッチングエンジンとそのネットワーク侵入検知への応用 International Conference on Field Programmable Technology,pp.297-300 (Co-authored) 2008/12/07
Papers	バイリニア補間法を用いた数値計算回路 International Conference on Field Programmable Logic and Applications,pp.463-466 (Co-authored) 2008/09/08
Papers	二変数関数の再構成可能な数値計算回路 EUROMICRO Conference on Digital System Design Architectures, Methods, and Tools,pp.891-898 (Co-authored) 2008/09/03
Papers	Efficient FPGA-based hardware algorithms for approximate string matching The 23rd International Technical Conference on Circuits/Systems, Computers and Communications,pp.201-204 (Co-authored) 2008/07/06
Papers	EVMDDを用いた二変数初等関数の表現法と数値計算回路への応用 IEEE International Symposium on Multiple-Valued Logic (Co-authored) 2008/05/22
Papers	二次割当問題のためのシストリックアルゴリズムとそのFPGA実装 International Conference on Field Programmable Technology,pp.261-264 (Co-authored) 2007/12/12
Papers	Design and FPGA implementation of a high-speed string matching engine Workshop on Synthesis And System Integration of Mixed Information technologies,pp.122-129 (Co-authored) 2007/10/15
Papers	FPGA実装に適した多項式近似に基づく数値計算回路の設計法 EUROMICRO Conference on Digital System Design Architectures, Methods, and Tools,pp.280-287 (Co-authored) 2007/08/29
Papers	A parallel multistage metaheuristic algorithm for VLSI floorplanning International Conference on Parallel & Distributed Processing Techniques & Applications (2),pp.801-807 (Co-authored) 2007/06/25
Papers	EVMDDを用いた初等関数の表現法 IEEE International Symposium on Multiple-Valued Logic (Co-authored) 2007/05/14
Papers	重みつき二分決定グラフを用いた数値計算回路アジア太平洋設計自動化会議,pp.535-540 (Co-authored) 2007/01/23
Papers	二次割当問題に対するタブー探索法のFPGA実装 International Conference on Field Programmable Technology,pp.269-272 (Co-authored) 2006/12/13
Papers	BMDを用いた初等関数の表現法 IEEE International Symposium on Multiple-Valued Logic (Co-authored) 2006/05/17
Papers	A parallel implementation of a genetic algorithm-based floorplanning method on PC clusters Workshop on Synthesis And System Integration of Mixed Information technologies,pp.404-411 (Co-authored) 2006/04/03
Papers	二次近似法に基づくプログラマブル数値計算回路の構成とその合成法 Asia and South Pacific Design Automation Conference,pp.378-383 (Co-authored) 2006/01/24
Papers	プログラマブル数値計算回路のアーキテクチャとその合成法 International Conference on Field Programmable Logic and Applications,pp.118-123 (Co-authored) 2005/08/24
Papers	信号線値を正当化するための最小キューブの抽出について Informal digest of papers for IEEE European Test Symposium,pp.79-84 (Co-authored) 2005/05/23
Papers	与えられた入力ベクトルからの最小リテラルを持ったキューブの抽出について Workshop on RTL and High Level Testing,pp.71-76 (Co-authored) 2004/11/11
Papers	決定グラフにおける最長パス長の最小化について International Workshop on Logic and Synthesis,pp.28-35 (Co-authored) 2004/06/02
Papers	ヘテロジニアスMDDにおける平均パス長の最小化について IEEE International Symposium on Multiple-Valued Logic,pp.216-222 (Co-authored) 2004/05/19
Papers	ヘテロジニアスMDDのメモリ量最小化 Asia and South Pacific Design Automation Conference,pp.872-875 (Co-authored) 2004/01/27
Papers	変数順序の変更によるBDDにおける平均パス長の最小化 International Workshop on Logic and Synthesis,pp.207-213 (Co-authored) 2003/05/28
Papers	ヘテロジニアスMDDを用いた論理関数のコンパクトな表現法 IEEE International Symposium on Multiple-Valued Logic,pp.247-255 (Co-authored) 2003/05/16
Papers	ヘテロジニアスMDDを用いた組み込みシステム用のコード生成 Workshop on Synthesis And System Integration of Mixed Information technologies,pp.258-264 (Co-authored) 2003/04/03
Papers	QRMDDを用いた論理関数の表現法 IEEE International Symposium on Multiple-Valued Logic,pp.261-267 (Co-authored) 2002/05/15
Papers	BDDを用いた多出力関数のコンパクトな表現法と組み込みシステムへの応用 IFIP VLSI-SOC'01,pp.406-411 (Co-authored) 2001/12/03
Papers	A Consideration on Benchmark Generation Based on Equivalence Classes in Maximally Asymmetric Functions IEICE MVL technical report,pp.50-57 (Co-authored) 2024/01/07
Papers	A Proposal of Equivalence Classes in Maximally Asymmetric Functions Note on Multiple-Valued Logic in Japan,pp.1-1-1-6 (Co-authored) 2023/09/23
Papers	A Feature Vector Considering Characteristics of Optical System for Lithography Hotspot Detection IEICE technical report,pp.VLD2022-81, 49-54 (Co-authored) 2023/03/01
Papers	On Row-Shift Decomposability for Symmetric Index Generation Functions Note on Multiple-Valued Logic in Japan,pp.10-1-10-6 (Co-authored) 2022/09/18
Papers	A Study on Anomaly Detection Based on Multiple-Valued Decision Trees in a Hyper Spectral Image Note on Multiple-Valued Logic in Japan,pp.5-1-5-8 (Co-authored) 2022/09/17
Papers	On Efficient Automatic Instance Generation Methods for Number Link Note on Multiple-Valued Logic in Japan,pp.9-1-9-7 (Co-authored) 2021/09/12
Papers	Proposal of Decision and Generation Methods for Maximally Asymmetric Multiple-Valued Functions Note on Multiple-Valued Logic in Japan,pp.4-1-4-8 (Co-authored) 2020/09/05
Papers	Characteristic Analyses and Generation of Maximally Asymmetric Functions IEICE technical report,pp.VLD2020-7, 35-40 (Co-authored) 2020/06/18
Papers	On Equivalence Classes of Index Generation Functions Based on Their Row-Shift Decompositions IEICE MVL technical report,pp.24-29 (Co-authored) 2020/01/11
Papers	On Row-Shift Decomposability of Index Generation Functions Note on Multiple-Valued Logic in Japan Research Group of Multiple-Valued Logic,pp.No. 13, 1-6 (Co-authored) 2019/09/15
Papers	A Study on Multi-Valued Isolation Forests Note on Multiple-Valued Logic in Japan Research Group of Multiple-Valued Logic,pp.No. 12, 1-8 (Co-authored) 2019/09/15
Papers	A Monte-Carlo Tree Search Based Method to Produce High Quality Initial Solutions for Motif Extraction Problem Note on Multiple-Valued Logic in Japan Research Group of Multiple-Valued Logic,pp.No. 2, 1-6 (Sole-authored) 2018/09/15
Papers	Development of Experimental Robot and Laboratory Curriculum for Education of Embedded Technology and Network Technology,pp.373-374 (Co-authored) 2018/03/13
Papers	A Motif Extraction Method Using Monte-Carlo Tree Search and its Experimental Evaluation IEICE technical report,pp.VLD2017-108, 115-120 (Co-authored) 2018/03/01
Papers	A Study of Lithography Hotspot Detection Method Based on Feature Vectors Considering Distances between Wires IEICE technical report,pp.VLD2017-105, 97-105 (Co-authored) 2018/03/01
Papers	k-Nearest Neighbor Search Hardware Using Locality Sensitive Hashing for High-Dimensional Data IEICE technical report,pp.VLD2017-91, 13-18 (Co-authored) 2018/02/28
Papers	On Memory Size Reduction of Programmable Hardware for Random Forest based Network Intrusion Detection IEICE technical report,pp.VLD2017-90, 7-12 (Co-authored) 2018/02/28
Papers	On Fast Computation of RBF Approximate Function by FPGA Implementation IEICE technical report,pp.VLD2017-89, 1-6 (Co-authored) 2018/02/28
Papers	An Exact Solution for Optimum Linear Decomposition of Index Generation Functions Note on Multiple-Valued Logic in Japan Research Group of Multiple-Valued Logic,pp.No. 24, 1-8 (Sole-authored) 2017/09/17
Papers	An Implementation Method of Reconfigurable Network Intrusion Detection Systems Based on Random Forests IEICE technical report,pp.VLD2017-10, 37-42 (Co-authored) 2017/06/19
Papers	An Optimization Method for Automotive Engine Control Parameters Using Gradient Methods IEICE technical report,pp.VLD2017-9, 31-36 (Co-authored) 2017/06/19
Papers	Acceleration of a Hotspot Detection Method Based on Approximate String Matching for LSI Mask Pattern Using Table Reference IEICE technical report,pp.VLD2016-112, 61-66 (Co-authored) 2017/03/02
Papers	Generation of Optimum Screening Patterns for a Screening Circuit to Detect Network Intrusion IEICE technical report,pp.VLD2016-108, 37-42 (Co-authored) 2017/03/02
Papers	FPGA Implementation of Mahalanobis Distance-Based Outlier Detection for Streaming Data IEICE technical report,pp.RECONF2016-72, 141-146 (Co-authored) 2017/01/16
Papers	A Screening Circuit for Intrusion Detection of High-Speed Networks and its FPGA Implementation IEICE technical report,pp.VLD2015-119, 49-54 (Co-authored) 2016/03/01
Papers	A Parallel Algorithm for Realizing the MacCormack Scheme in Computational Fluid Dynamics and its FPGA Implementation IEICE technical report,pp.RECONF2015-75, 137-142 (Co-authored) 2016/01/20
Papers	GPGPU Implementation of the MSD Method for Outlier Detection and Its Experimental Evaluation IEICE technical report,pp.CPSY2015-115, 37-42 (Co-authored) 2016/01/19
Papers	On a Fast Method for Linear Decomposition of Index Generation Functions IEICE MVL technical report,pp.1-8 (Co-authored) 2016/01/09
Papers	On Regular Expression Matching Methods for Fast Network Intrusion Detection Systems with High Maintainability Technical Report on Functional Integrated Information System, IEICE,pp.1-1 (Co-authored) 2015/06/26
Papers	A Parallel Algorithm for Realizing the Lax-Friedrichs Scheme in Computational Fluid Dynamics and its FPGA Implementation IEICE technical report,pp.VLD2014-180, 153-158 (Co-authored) 2015/03/04
Papers	Implementation of Sparse Matrix-Vector Multiplication on GPU and Its Application to the Conjugate Gradient Method IEICE technical report,pp.CPSY2014-150, 181-186 (Co-authored) 2015/01/30
Papers	Intrusion Detection in High-Speed Networks with a Multi-Byte Transition NFA IEICE technical report,pp.RECONF2014-66, 133-138 (Co-authored) 2015/01/30
Papers	Faster Analysis of Multi-State Systems by a New Reduction Rule for EVMDDs IEICE MVL technical report,pp.1-8 (Co-authored) 2015/01/10
Papers	GPGPU Implementation of the Conjugate Gradient Method for Simultaneous Linear Equations and Its Experimental Evaluation Design Automation Symposium 2014,pp.227-232 (Co-authored) 2014/08/29
Papers	FPGA Implementation of the Conjugate Gradient Method for Simultaneous Linear Equations and Its Experimental Evaluation The 27th Workshop on Circuits and Systems,pp.80-85 (Co-authored) 2014/08/04
Papers	Fast Regular Expression Matching Using Dual Glushkov NFA Hokkaido University, Division of Computer Science, TCS Technical Reports (Co-authored) 2014/05/26
Papers	Parallel Tabu Search for the Motif Extraction Problem in Molecular Biology and its GPGPU Implementation IEICE technical report,pp.VLD2013-144, 61-66 (Co-authored) 2014/03/04
Papers	A unified software/reconfigurable hardware approach to solving the maximum clique problem of large graphs IEICE technical report,pp.RECONF2013-57, 7-12 (Co-authored) 2014/01/28
Papers	An Analysis Method of Multi-State Systems Considering Dependent Events Among Some Components IEICE MVL technical report,pp.MVL14-10, 70-77 (Co-authored) 2014/01/12
Papers	ILP-Based Placement and Routing Method for PLDs for Minimizing Critical Path Length IEICE technical report,pp.RECONF2013-49, 57-62 (Co-authored) 2013/11/28
Papers	A New Optimization Method of EVMDDs for Fast Analysis of Multi-State Systems Note on Multiple-Valued Logic in Japan Research Group of Multiple-Valued Logic,pp.No. 5, 1-8 (Co-authored) 2013/09/14
Papers	A Compact Regular Expression Matching Engine Using Partial Reconfiguration for Quick Pattern Updating The 26th Workshop on Circuits and Systems,pp.191-196 (Co-authored) 2013/07/29
Papers	A Parallel Global Routing Method Sharing Routing Regions for Multi-Core Processors IEICE technical report,pp.VLD2012-150, 83-88 (Co-authored) 2013/03/05
Papers	A Diagnosis Method of Multi-State Systems Using EVMDDs IEICE MVL technical report,pp.MVL13-13, 70-77 (Co-authored) 2013/01/13
Papers	A Hardware Algorithm Using Dynamically Partially Reconfigurable FPGA for Solving the Maximum Clique Problem of Large Graphs IEICE technical report,pp.RECONF2012-53, 33-38 (Co-authored) 2012/11/28
Papers	An ILP Formulation of Placement and Routing for PLDs IEICE technical report,pp.VLD2012-75, 93-98 (Co-authored) 2012/11/27
Papers	Analysis of Multi-State Systems with Multi-State Components Based on EVMDDs Note on Multiple-Valued Logic in Japan Research Group of Multiple-Valued Logic,pp.No. 22, 1-8 (Co-authored) 2012/09/16
Papers	A GPGPU Implementation of Approximate Regular Expression Matching Algorithm and Comparison with an FPGA Implementation IEICE technical report,pp.VLD2011-139, 115-120 (Co-authored) 2012/03/07
Papers	Implementation of Look-ahead Assertion for Pattern-independent Regular Expression Matching Engine IEICE technical report,pp.VLD2011-136, 97-102 (Co-authored) 2012/03/07
Papers	A Regular Expression Matching Engine Based on a Systolic Algorithm with a Pattern-Independent NFA for Network Intrusion Detection Forum on Information Technology 2011,pp.95-201 (Co-authored) 2011/09/09
Papers	Elementary Function Generators Based on Piecewise Arithmetic Transform IEICE MVL technical report,pp.MVL11-12, 66-72 (Co-authored) 2011/01/09
Papers	A Design Method for Two-Variable Discrete Functions Using Spline and Bilinear Interpolations IEICE MVL technical report,pp.MVL11-10, 54-61 (Co-authored) 2011/01/09
Papers	Solving a Class of Approximate String Matching Problems Using a One-Dimensional Systolic Algorithm IEICE MVL technical report,pp.MVL11-7, 31-37 (Co-authored) 2011/01/08
Papers	Floating-Point Mathematical Function Generators Using Piecewise-Split Multi-Valued Decision Diagrams Note on Multiple-Valued Logic in Japan Research Group of Multiple-Valued Logic,pp.No. 3, 1-9 (Co-authored) 2010/09/11
Papers	An Efficient Hadware Engine for Regular Expression Matching With Nested Kleene Operators Note on Multiple-Valued Logic in Japan Research Group of Multiple-Valued Logic,pp.No. 2, 1-9 (Co-authored) 2010/09/11
Papers	A Study on High-Speed Algorithm for Solving Approximation String Matching Problems and Its FPGA Implementation Note on Multiple-Valued Logic in Japan Research Group of Multiple-Valued Logic,pp.No. 1, 1-9 (Co-authored) 2010/09/11
Papers	An Approximate Regular Expression Matching Algorithm for High-Speed Text Search and Its FPGA Implementation Forum on Information Technology 2010,pp.69-74 (Co-authored) 2010/09/08
Papers	Regular Expression Pattern Matching Hardware for Realizing Iteration of Strings Using Quantifiers IEICE technical report,pp.RECONF2009-76, 137-142 (Co-authored) 2010/01/27
Papers	LSI Floorplanning Based on Parallel Simulated Annealing for Multicore Processors IPSJ Symposium Series,pp.61-66 (Co-authored) 2009/08/26
Papers	An architecture of regular expression matching machine for NIDS and its FPGA implementation IEICE technical report,pp.RECONF2008-87, 189-194 (Co-authored) 2009/01/29
Papers	Floating-Point Representations of Monotone Elementary Functions Using MDDs IEICE MVL technical report,pp.MVL09-14, 76-85 (Co-authored) 2009/01/10
Papers	On programmable two-variable numerical function generators IEICE technical report,pp.RECONF2008-49, 57-62 (Co-authored) 2008/11/17
Papers	EVMDD-Based Representations of Two-Variable Mathematical Functions and Their Applications of Function Generators Note on Multiple-Valued Logic in Japan Research Group of Multiple-Valued Logic,pp.No. 10, 1-9 (Co-authored) 2008/09/11
Papers	FPGA Implementation of a String Matching Machine and Its Application to Network Intrusion Detection Systems IPSJ Symposium Series,pp.91-96 (Co-authored) 2008/08/26
Papers	A Regular Expression String Matching Machine Allowing Pattern Setting During Execution Time and Its FPGA Implementation IEICE technical report,pp.RECONF2007-61, 61-66 (Co-authored) 2008/01/16
Papers	Solving the Quadratic Assignment Problem by Hardware Based on a Systolic Algorithm IEICE technical report,pp.RECONF2007-60, 55-60 (Co-authored) 2008/01/16
Papers	A parallel algorithm based on genetic algorithm and tabu search for LSI floorplanning and its implementation on a PC cluster IEICE technical report,pp.VLD2006-90, 31-36 (Co-authored) 2007/01/17
Papers	A hardware algorithm for the quadratic assignment problem based on tabu search using FPGAs IEICE technical report,pp.RECONF2006-62, 37-42 (Co-authored) 2007/01/17
Papers	Architecture for numerical function generators using EVBDDs IEICE technical report,pp.RECONF2006-48, 25-30 (Co-authored) 2006/11/28
Papers	Numerical function generators based on polynomial approximation suitable for FPGA implementation IEICE technical report,pp.RECONF2006-29, 13-18 (Co-authored) 2006/09/14
Papers	Representations of elementary functions using BMDs and their applications to numerical function generators Note on Multiple-Valued Logic in Japan Research Group of Multiple-Valued Logic,pp.No. 10, 1-6 (Co-authored) 2006/08/21
Papers	Programmable numerical function generators based on quadratic approximation: architecture and synthesis method IEICE technical report,pp.VLD2005-91, 25-30 (Co-authored) 2006/01/17
Papers	Programmable numerical function generators: architectures and synthesis method IEICE technical report,pp.RECONF2005-41, 1-6 (Co-authored) 2005/09/15
Papers	On the extraction of a minimum cube to justify signal line values from a given input vector IEICE technical report,pp.VLD2004-77, 97-102 (Co-authored) 2004/12/01
Papers	Realization of multiple-output functions by sequential Look-Up Table cascades IEICE technical report,pp.VLD2003-127, 13-18 (Co-authored) 2004/01/22
Papers	Minimization of average path lengths for heterogeneous MDDs IEICE technical report,pp.VLD2003-107, 223-228 (Co-authored) 2003/11/27
Papers	Compact representations of logic functions using heterogeneous MDDs IEICE technical report,pp.VLD2002-98, 97-102 (Co-authored) 2002/11/27
Papers	Representations of logic functions using QRMDDs IEICE technical report,pp.VLD2001-142, 77-84 (Co-authored) 2002/01/23
Papers	Compact representations of BDDs for multiple-output functions and their optimization IEICE technical report,pp.VLD2001-100, 67-72 (Co-authored) 2001/11/28