Book and thesis
Papers
A prototype design of reconfigurable device SePLD in 0.6um CMOS process Proc. of the ITC CSCC 2017,pp.579-582 (Co-authored) 2017/07/05
Papers
Development of a TRAX Artificial Intelligence Algorithm using Path and Edge Proc. of International Conference on Field Programmable Technology (FPT'15),pp.256-259 (Co-authored) 2015/12/07
Papers
Design Consideration of a Secure Sensor Chip for Home Cancer Examination Proc. of the ITC CSCC 2015,pp.588-591 (Co-authored) 2015/07/01
Papers
Proposal of a small logic block for a reconfigurable device with flexibility on mapping of routing and logic cell Proc. of the ITC CSCC 2015,pp.511-514 (Co-authored) 2015/07/01
Papers
Requirement of a standard programming model for reconfigurable processors NII Shonan Meeting Report No.2012-11 The NII Shonan Configurable Computing Workshop",pp.11 (Sole-authored) 2012/11
Papers
A Physical Design Method for a New Memory-based Reconfigurable Architecture without Switch Blocks IEICE Trans. on Information and Systems E95-D (2),pp.324-334 (Co-authored) 2012/02
Papers
Design Consideration for Reconfigurable Processor DS-HIE Proc. of the 2011 International SoC Design Conference, 2011,pp.187-190 (Co-authored) 2011/11
Papers
EDA Environment for Evaluating a New Switch-Block- Free Reconfigurable Architecture Proc. of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig),pp.448-454 (Co-authored) 2011/11
Papers
Memory Array Based PLD Architecture for High-Density Logic Mapping – Implementation of First Demo Chip –, Proc. of the IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XIV), Poster1,pp.1 (Co-authored) 2011/04
Papers
Comparison of Bit Serial Computation with Bit Parallel Computation for Reconfigurable Processor Proc. of the 6th Interna-tional Workshop on Applied Reconfigurable Computing (ARC 2010),pp.388-393 (Co-authored) 2010/03
Papers
Evaluation of Compact High-Throughput Reconfigurable Architecture Based on Bit-Serial Computation, Proc. of the International Conference on Field-Programmable Technology (ICFPT2008),,pp.273-276 (Co-authored) 2008/12
Papers
Exploring Compact Design on High Throughput Coarse Grained Reconfigurable Architectures Proc. of the 18th International Conference on Field Programmable Logic and Applications (FPL2008),pp.543-546 (Co-authored) 2008/09
Papers
An Adaptive Compiler Method for Scheduling and Place-and-Route for VLIW-based Dynamic Reconfigurable, Proc. of the 12th WSEAS International Conference on COMPUTERS,pp.61-69 (Co-authored) 2008/07
Papers
Development and Evaluation of Raytracing Acceleration Engine with Bit Serial Arithmetic Units Proc. of the Interna-tional Technical Con-ference on Cir-cuits/Systems Com-puters and Communica-tions (ITC-CSCC 2008),pp.237-240 (Co-authored) 2008/07
Papers
Development of Compiler which Supports High-level Programming Language for Dynamic Reconfigurable Architecture DS-HIE Proc. of the Interna-tional Technical Con-ference on Cir-cuits/Systems Com-puters and Communica-tions (ITC-CSCC 2008),pp.405-408 (Co-authored) 2008/07
Papers
Development of Heterogenous Multi-core Processor "Hy-DiSC" with Dynamic Reconfigurable Processor Proc. of the Interna-tional Technical Con-ference on Cir-cuits/Systems Com-puters and Communica-tions (ITC-CSCC 2008),pp.145-148 (Co-authored) 2008/07
Papers
Low Cost PLD with High Speed Partial Reconfiguration Proc. of the Interna-tional Technical Con-ference on Cir-cuits/Systems Com-puters and Communica-tions (ITC-CSCC 2008),pp.557-560 (Co-authored) 2008/07
Papers
A PLD architecture for high performance computing Proc. of the International Workshop on Innovative Archi-tecture for Future Generation High-Performance Processors and Systems (IWIA'08),pp.35-42 (Co-authored) 2008/01
Papers
Development of DS-HIE Architecture Proc. of the Interna-tional Technical Con-ference on Cir-cuits/Systems Com-puters and Communica-tions (ITC-CSCC 2007) 1,pp.47-48 (Co-authored) 2007/07
Papers
Reconfigurable Processor 'PARS' and its Compiler Proc. of the International Workshop on Innovative Archi-tecture for Future Generation High-Performance Processors and Systems (IWIA'07),pp.91-100 (Co-authored) 2007/01
Papers
Unified data/instruction cache with hierarchical multi-port architecture and hidden precharge pipeline Proc. of the 2006 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS2006),,pp.1299-1302 (Co-authored) 2006/12
Papers
Multi-bank register file for increased performance of highly-parallel processors, Proc. of the 32nd European Solid-State Circuits Conference (ESSCIRC2006),pp.154-157 (Co-authored) 2006/09
Papers
Performance Evaluation of Superscalar Processor with Multi-Bank Register File and an Implementation Result, WSEAS Transactions on Computer 9 (5),pp.1993-2000 (Co-authored) 2006/09
Papers
Performance Evaluation of Superscalar Processor with Multi-Bank Register File Using SPEC2000, Proc. of the 10th WSEAS International Conference on COMPUTERS,pp.1062-1067 (Co-authored) 2006/07
Papers
A Design and Evaluation of Low Energy Processor by Variable Stages Pipeline Technique,pp.231-242 (Co-authored) 2006/05
Papers
Consideration of high precision FFT logic with digit-serial floating point unit IPSJ Techenical Report, 2005-ARC-165,pp.33-38 (Co-authored) 2005/12
Papers
Evaluation of Branch Predictor for Unified Instruction Trace Cache IPSJ Techenical Report, 2005-ARC-165,pp.75-80 (Co-authored) 2005/12
Papers
Place and Route Processing in Back End Compiler for Reconfigurable Architecture 'PARS' IEICE Trans. Inf. & Syst., RECONF2005-30,pp.1-6 (Co-authored) 2005/09
Papers
A Design of Prototype Low Energy Processor by Variable Stages Pipeline Technique Proc. of the International Technical Conference on Circuits/Systems Computers and Communications (ITC-CSCC2005) 2,pp.561-562 (Co-authored) 2005/07
Papers
Evaluation of the n Bit-Serial Arithmetic Units in Consideration of Trade-off between Area and Performance Proc. of the International Technical Conference on Circuits/Systems Computers and Communications (ITC-CSCC2005) 3,pp.943-944 (Co-authored) 2005/07
Papers
Design of Superscalar Processor with Multi-bank Register File Proc. of the IEEE International Symposium on Circuits and Systems, 2005 (ISCAS2005),pp.3507-3510 (Co-authored) 2005/05
Papers
Code Scheduling in Consideration of Place and Wire in Back End Compiler for PARS IEICE Trans. Inf. & Syst., RECONF2005-13,pp.73-78 (Co-authored) 2005/05
Papers
Superscalar Processor with Multi-Bank Register File Proc. of the 8th International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA2005),pp.3-12 (Co-authored) 2005/01
Papers
A Coarse-Grained Reconfigurable Architecture with Low Cost Configuration Data Compression Mechanism Proc. of the IEEE International Conference on Field-Programmable Technology (FPT2003),pp.311-314 (Co-authored) 2003/12
Papers
PARS Architecture: A Reconfigurable Architecture with Generalized Execution Model - Design and Implementation of its Prototype Processor IEICE Trans. on Information and Systems E86-D (5),pp.830-840 (Co-authored) 2003/05
Papers
A Generalized Execution Model for Programming on Reconfigurable Architectures and an Architecture Supporting the Model Proc. of the Conference on Field Programmable Logic and Applications (FPL2002) 2438,pp.434-443 (Co-authored) 2002/09
Papers
Implementation of the Reconfigurable Processor with Ability of Every-cycle Reconfiguration and Execution Proc. of the IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips V),pp.162 (Co-authored) 2002/04