Faculty Information - Ichihara Hideyuki |

Ichihara Hideyuki

Department / Course Hiroshima City University Graduate School Graduate School of Information Sciences Major in Computer and Network Engineering

Hiroshima City University Faculty of Information Sciences Department of Computer and Network Engineering

Job Professor

Book and thesis
Papers	On Accuracy Enhancement of No-Reference Error-Tolerability Testing for Images in Object Detection Applications Based on RGB Channel Characteristics IEEE Proc. ITC-Asia (Co-authored) 2024/08
Papers	On the Estimation of Multi-Cloud Computational Resources Based on the Analysis Methodology of Inventory Systems IEICE Trans. Communications (Japanese Edition) (No. 2),pp.63-71 (Co-authored) 2024/02
Papers	Reliability Analysis of Approximate Multipliers with Recovery Schemes (Co-authored) 2023/10
Papers	An Improvement of the No-Reference Test Scheme Based on False Edge Detection for Image Processing Application Proc. IEEE International Test Conference in Asia (Co-authored) 2022/08
Papers	A Design of Approximate Voting Schemes for Fail-Operational Systems Proc. 22nd IEEE Asian Test Symp. (Co-authored) 2021/11
Papers	A Design of Reliable Linear FSMs with Equivalent States in Stochastic Computing IEEE Proc. of International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (Co-authored) 2021/10
Papers	Transient Fault Tolerant State Assignment for Stochastic Computing Based on Linear Finite State Machines IEICE Trans. Fundamentals E103-A (12),pp.1464-1471 (Co-authored) 2020/12
Papers	Experimental Evaluation of the No-Reference Test Based of False Edge Detection for Image Processing Application Digest of Papers 21st IEEE Workshop on RTL and High Level Testing (Co-authored) 2020/11
Papers	Extension of an Approximate Voting Scheme IDMR for Fail-Operational Systems Digest of Papers 20th IEEE Workshop on RTL and High Level Testing (Co-authored) 2019/12
Papers	State Encoding with Stochastic Numbers for Transient Fault Tolerant Linear Finite State Machines IEEE Proc. of International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (Co-authored) 2019/10
Papers	An empirical approach to RTL scan path design focusing on structural interpretation in logic synthesis Proc. 3rd IEEE International Test Conference in Asia (Co-authored) 2019/09
Papers	Effective Utilization of Register-Transfer Paths Based on Enhancing Multiplexer Functions in RTL Scan Design Digest of Papers 19th IEEE Workshop on RTL and High Level Testing (Co-authored) 2018/10
Papers	Experimental evaluation of test cost reduction by scan chain testing in RTL scan circuits Digest of Papers 18th IEEE Workshop on RTL and High Level Testing (Co-authored) 2017/11
Papers	State Assignment for Fault Tolerant Stochastic Computing with Linear Finite State Machines Proc. ITC-Asia (Co-authored) 2017/09
Papers	Exploration of Four-Phase Dual-Rail Asynchronous RTL Design for Delay-Robustness Digest of Papers 17th IEEE Workshop on RTL and High Level Testing (Co-authored) 2016/11
Papers	Impact of State Assignment on Error Resilient Stochastic Computing with Linear Finite State Machines Digest of Papers 17th IEEE Workshop on RTL and High Level Testing (Co-authored) 2016/11
Papers	Stochastic Number Generation with Internal Signals of Logic Circuits Proc. SASIMI (Co-authored) 2016/10
Papers	Compact and Accurate Digital Filters Based on Stochastic Computing Trans. on Emerging Topics in Comp. (Co-authored) 2016/09
Papers	A Prototype of a Hardware SAT Solver for Similar Large Instances and Its Application to Test Generation Digest of Papers 16th IEEE Workshop on RTL and High Level Testing (WRTLT '15) (Co-authored) 2015/11
Papers	Logic Simplification by Minterm Complement for Error Tolerant Application Proc. International Conference on Computer Design (Co-authored) 2015/10
Papers	A Fault Tolerant Response Analyzer with Self-Error-Correction Capability Proc. European Test Symp. (Co-authored) 2015/05
Papers	A practical approach for logic simplification based on fault acceptability for error tolerant application Proc. 20th IEEE European Test Symposium (ETS '15) (Co-authored) 2015/05
Papers	Designing area-efficient controllers for multi-cycle transient fault tolerant systems Proc. 20th IEEE European Test Symposium (ETS '15) (Co-authored) 2015/05
Papers	A controller design in high-level synthesis for long duration transient fault tolerance Digest of Papers 15th IEEE Workshop on RTL and High Level Testing (WRTLT '14) (Co-authored) 2014/11
Papers	A System-Error-Rate-Oriented Approach to Test Generation for Effective Yield Maximization IEEE International Workshop on Reliability Aware System Design and Test (Co-authored) 2014/01
Papers	A scheduling algorithm in datapath synthesis for long duration transient fault tolerance Proc. 17th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT '14) (Co-authored) 2014
Papers	Compact and Accurate Stochastic Circuits with Shared Random Number Sources Proc. IEEE International Conference on Computer Design (Co-authored) 2014
Papers	A Design of Error Correctable Response Analyzers for Reliable Built-in Self-test Digest of Papers 14th IEEE Workshop on RTL and High Level Testing (Co-authored) 2013/11
Papers	A Heuristic Algorithm for Operational Unit Binding to Synthesize Multi-Cycle Transient Fault Tolerant Datapaths Digest of Papers 14th IEEE Workshop on RTL and High Level Testing (Co-authored) 2013/11
Papers	A Transient Fault Tolerant Test Pattern Generator for On-line Built-in Self-test Proc. 22nd IEEE Asian Test Symp. (Co-authored) 2013
Papers	Exact and Heuristic Methods of Generating Compact Tests for Hold-time Violations Digest Papers of Workshop on RTL and High Level Testing (Co-authored) 2012/11
Papers	Concurrent Testable Response Analyzer with Cyclic Code in Built-in Self Test IEICE Trans. D,pp.496-505 (Co-authored) 2012/03
Papers	A Study on Error Correctable Test Pattern Generator for Reliable Built-in Self Test Workshop on RTL and High Level Testing (Co-authored) 2012
Papers	A technique for SAT-based test generation through history of reusing solutions Proc. 17th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI ’12) (Co-authored) 2012
Papers	Modeling Economics of LSI Design and Manufacturing for Test Design Selection Proc. ICCD (Co-authored) 2012
Papers	Utilizing register transfer level false paths for circuit optimization with a logic synthesis tool Proc. IEEE Asia Pacific Conference on Circuits and Systems (Co-authored) 2012
Papers	Hybrid Test Application in Partial Skewed-load Scan Design IEICE Trans. Fundamentals E94-A (12),pp.2571-2578 (Co-authored) 2011/12
Papers	An approach to hardware SAT solvers for test generation based on instance similarity 12th IEEE Workshop on RTL and High Level Testing (Co-authored) 2011/11
Papers	Test Compression Based on Lossy Image Encoding Proc. IEEE Asian Test Symp. (ATS),pp.273-278 (Co-authored) 2011/11
Papers	High-Level Synthesis for Multi-Cycle Transient Fault Tolerant Datapaths Proc. IEEE Int. On-Line Testing Symp. (IOLTS),pp.13-18 (Co-authored) 2011/07
Papers	A New Class of Acyclically Testable Sequential Circuits with Multiplexers Workshop on RTL and High Level Testing (Co-authored) 2010/12
Papers	Experimental Evaluation of Hybrid RTL Scan Design Workshop on RTL and High Level Testing (Co-authored) 2010/12
Papers	A Design of Response Analyzers with Self-Distinguishability in Built-in Self-Test Proc. International Symposium on Communications and Information Technologies (ISCIT),pp.732-735 (Co-authored) 2010/10
Papers	A Practical Threshold Test Generation for Error Tolerant Application IEICE Trans. Inf. & Syst. E93-D (10),pp.2776-2782 (Co-authored) 2010/10
Papers	An FPGA-Based Fail-soft System with Adaptive Reconfiguration Proc. 16th IEEE International On-Line Testing Symposium,pp.127-132 (Co-authored) 2010/07
Papers	Design and Optimization of Transparency-Based TAM for SoC Test IEICE Trans. Inf. & Syst. E93-D (6),pp.1549-1559 (Co-authored) 2010/06
Papers	Hybrid Test Application in Hybrid Delay Scan Design EEE Proc. ETS,pp.247 (Co-authored) 2010/05
Papers	A Fast Threshold Test Generation Algorithm Based on 5-Valued Logic IEEE Proc. DELTA,pp.345-349 (Co-authored) 2010/01
Papers	A Yield Model of Design for Testability and Repairability IEEE Proc. RASDAT (Co-authored) 2010/01
Papers	A Design of Concurrently Testable Response Analyzers in Built-in Self-Test IEEE Digest Papers of WRTLT,pp.88-93 (Co-authored) 2009/11
Papers	A Practical Approach to Threshold Test Generation for Error Tolerant Circuits IEEE Proc. ATS (Co-authored) 2009/11
Papers	Reliability and Performance of FPGA-Based Fault Tolerant Systems (Co-authored) 2009/10
Papers	Test Data Reduction by Test Point Insertion Based on Necessary Assignment Proc. European Test Symposium (CD-ROM) (Co-authored) 2009/05
Papers	Test Generation and DFT Based on Partial Thru Testability Proc. European Test Symposium (CD-ROM) 2009/05
Papers	A Method for Test Data Reduction by Test Point Insertion Based on Necessary Assignment Digest of Papers of 9th Workshop on RTL and High-Level Testing(WRTLT'08),pp.105-110 (Co-authored) 2008/11
Papers	Reliability and Performance of FPGA-Based Fault Tolerant Systems Digest of Papers of 9th Workshop on RTL and High-Level Testing (WRTLT'08),pp.75-80 (Co-authored) 2008/11
Papers	A Self-Test of Dynamically Reconfigurable Processors with Test Frames IEICE Trans. Inf. & Syst. E91 (3),pp.756-762 (Co-authored) 2008/03
Papers	An Architecture of Embedded Decompressor with Reconfigurability for Test Compression IEICE Trans. Inf. & Syst. E91 (3),pp.713-719 (Co-authored) 2008/03
Papers	An Extended Class of Acyclically Testable Circuits Dig. of Papers of 8th Workshop on RTL and High-Level Testing (WRTLT'07) (Co-authored) 2007/10
Papers	Test Compression / Decompression Based on JPEG VLC Algorithm Proc. Asian Test Symp.,pp.87-90 (Co-authored) 2007/10
Papers	A Variable-length Coding Adjustable for Compressed Test Application IEICE Trans. Inf. & Syst. E90 (8),pp.1235-1242 (Co-authored) 2007/08
Papers	Optimal Contexts for the Self-Test of Coarse Grain Dynamically Reconfigurable Processors Proc. European Test Symp.,pp.117-122 (Co-authored) 2007/05
Papers	TAM Design and Optimization for Transparency-based SoC Test Proc. VLSI Test Symp.,pp.381-386 (Co-authored) 2007/05
Papers	An Optimal Test Bus Design for Transparency-based SoC Test Digest Papers of Workshop on RTL and High Level Testing 47,pp.21-26 (Co-authored) 2006/11
Papers	A Statistical Error Model for the Image Sensor and Its Testing IEICE Trans. Inf. & Syst. (Co-authored) 2006/08
Papers	An Adaptive Decompressor for Test Application with Variable-Length Coding IPSJ Journal 47 (6) (Co-authored) 2006/06
Papers	A Reconfigurable Embedded Decompressor for Test Compression Proc. IEEE International Workshop on Electronic Design, Test & Applications (DELTA2006),pp.301-306 (Co-authored) 2006/01
Papers	An Effective Design for Hierarchical Test Generation Based on Strong Testability Proc. IEEE Asian Test Symposium,pp.288--293 (Co-authored) 2005/12
Papers	A method for designing hierarchically testable datapaths based on fixed-control testability Digest Papers of Workshop on RTL and High Level Testing,pp.174-179 (Co-authored) 2005/07
Papers	A Test Generation for Compressible and Compact Test Sets IEICE Trans. D-I,pp.1021--1028 (Co-authored) 2005/06
Papers	A Huffman-based coding with efficient test application Proc. ASP-DAC,pp.75--78 (Co-authored) 2005/01
Papers	A Test Compression Algorithm for Reducing Test Application Time Digest Papers of 5th Workshop on RTL and High Level Testing (Co-authored) 2004/11
Papers	A Test Decompression Scheme for Variable-Length Coding IEEE Proc. Asian Test Symp.,pp.426-431 (Co-authored) 2004/11
Papers	A Method of Test Generation for Acyclic Sequential Circuits Using Single Stuck-at Fault Combinational ATPG IEICE Trans. Fundamentals E86-A (12),pp.3072-3078 (Co-authored) 2003/12
Papers	An Improvement of a Test Plan Generation Algorithm for Hierarchical Test Based on Strong Testability Digest Papers of Workshop on RTL and High Level Testing,pp.37-42 (Co-authored) 2003/11
Papers	Test Response Compression Based on Huffman Coding Proc. Asian Test symposium,pp.446--449 (Co-authored) 2003/11
Papers	Test Generation for Acyclic Sequential Circuits with Single Stuck-at Fault Combinational ATPG Proc. DATE03,pp.1180--1181 (Co-authored) 2003/03
Papers	Channel Width Test Data Compression under a Limited Number of Test Inputs and Outputs Proc. the 16th International Conference on VLSI Design,pp.329--334 (Co-authored) 2003/01
Papers	Test Generation for Test Compression Based on Statistical Coding IEICE Trans. Inf. & Syst E85-D (10),pp.1466-1473 (Co-authored) 2002/10
Papers	Generating Small Test Sets for Test Compression / Decompression Using Statistical Coding The First International Workshop on Electronic Design, Test & Applications,pp.396--400 (Co-authored) 2002/01
Papers	Dynamic Test Compression Using Statistical Coding Proc. The Tenth Asian Test Symposium,pp.143--148 (Co-authored) 2001/11
Papers	On Processing Order for Obtaining Implication Relations in Static Learning IEICE Trans. Inf. & Syst. E83-D (10),pp.1908-1911 (Co-authored) 2000/10
Papers	Test Transformation to improve Compaction by Statistical Encoding The VLSI Design 2000 Conference,pp.294--299 (Co-authored) 2000/01
Papers	On An Effective Selection of IDDQ Measurement Vectors for Sequential Circuits The Eighth Asian Test Symposium,pp.147--152 (Co-authored) 1999/11
Papers	On Test Pattern Selection with a Limited Number of Tests The transaction of the institute of Electronics Information and Communication Engineers D-I,pp.861-868 (Co-authored) 1999/07
Papers	On test generation with a Limited Number of Tests Proc. Ninth Great Lakes Symposium on VLSI,pp.12-15 (Co-authored) 1999/03
Papers	An Efficient Procedure for Obtaining Implication Relations and Its Application to Redundancy Identif Proc. The Seventh Asian Test Symposium,pp.58--63 (Co-authored) 1998
Papers	On Acceleration of Logic Circuit Optimization Using Implication Relations Proc. The Sixth Asian Test Symposium,pp.222--227 (Co-authored) 1997/12
Papers	On Invariant Implication Relations for Removing-Partial Circuits The transactions of the institute of electronics, information and communication engineers D-I,pp.1037-1045 (Co-authored) 1996/12