Faculty Information - Inoue Tomoo |

Inoue Tomoo

Department / Course Hiroshima City University Graduate School Graduate School of Information Sciences Major in Computer and Network Engineering

Hiroshima City University Faculty of Information Sciences Department of Computer and Network Engineering

Job Professor

Book and thesis
Papers	On Accuracy Enhancement of No-Reference Error-Tolerability Testing for Images in Object Detection Applications Based on RGB Channel Characteristics IEEE Proceedings of 2024 IEEE International Test Conference in Asia (ITC-Asia) (Co-authored) 2024/08
Papers	Reliability Analysis of Approximate Multipliers with Recovery Schemes IEEE Proc. Asian Test Symposium (Co-authored) 2023/10
Papers	An Improvement of the No-Reference Test Scheme Based on False Edge Detection for Image Processing Application Porc. ITC-Asia (Co-authored) 2022/08
Papers	A Design of Approximate Voting Schemes for Fail-Operational Systems IEEE Proc. Asian Test Symposium (Co-authored) 2021/11
Papers	A Design of Multipliers with Approximate Adders and Compensators According to the Accuracy Required for Applications IEICE Trans. Inf.& Syst. (Co-authored) 2021/07
Papers	A Design of Fully Stochastic Computing Neurons Focused on the Gain of Sigmoid Functions IEICE Trans. Inf.& Syst. (Co-authored) 2021/07
Papers	Experimental Evaluation of the No-Reference Test Based of False Edge Detection for Image Processing Application Digest of Papers 21th IEEE Workshop on RTL and High Level Testing (Co-authored) 2020/11
Papers	Transient Fault Tolerant State Assignment for Stochastic Computing Based on Linear Finite State Machine IEICE Trans. Fundamentals, Vol. E103-A, No. 12, pp. 1464-1471, 2020 E103-A (12),pp.1464-1471 (Co-authored) 2020
Papers	An empirical approach to RTL scan path design focusing on structural interpretation in logic synthesis Proc. 3rd IEEE International Test Conference in Asia (ITC-Asia '19),pp.55-60 (Co-authored) 2019/09
Papers	Extension of an Approximate Voting Scheme IDMR for Fail-Operational Systems Digest of Papers 20th IEEE Workshop on RTL and High Level Testing (WRTLT '19) (Co-authored) 2019
Papers	State Encoding with Stochastic Numbers for Transient Fault Tolerant Linear Finite State Machines IEEE Proc. of International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (Co-authored) 2019
Papers	Effective Utilization of Register-Transfer Paths Based on Enhancing Multiplexer Functions in RTL Scan Design Digest of Papers 19th IEEE Workshop on RTL and High Level Testing (WRTLT '18) (Co-authored) 2018/10
Papers	Experimental evaluation of test cost reduction by scan chain testing in RTL scan circuits Digest of Papers 18th IEEE Workshop on RTL and High Level Testing (WRTLT '17) (Co-authored) 2017/11
Papers	State Assignment for Fault Tolerant Stochastic Computing with Linear Finite State Machines Proc. ITC-Asia Proc. 1st IEEE International Test Conference in Asia (ITC-Asia '17) (Co-authored) 2017/09
Papers	Exploration of Four-Phase Dual-Rail Asynchronous RTL Design for Delay-Robustness Digest of Papers 17th IEEE Workshop on RTL and High Level Testing (Co-authored) 2016/11
Papers	Impact of State Assignment on Error Resilient Stochastic Computing with Linear Finite State Machines Digest of Papers 17th IEEE Workshop on RTL and High Level Testing (Co-authored) 2016/11
Papers	Stochastic Number Generation with Internal Signals of Logic Circuits Proc. Int'l Workshop SASMI (Co-authored) 2016/10
Papers	Compact and Accurate Digital Filters Based on Stochastic Computing Trans. on Emerging Topics in Comp. (99) (Co-authored) 2016/09
Papers	A Prototype of a Hardware SAT Solver for Similar Large Instances and Its Application to Test Generation Digest of Papers 16th IEEE Workshop on RTL and High Level Testing (Co-authored) 2015/11
Papers	Logic Simplification by Minterm Complement for Error Tolerant Application Proc. IEEE International Conference on Computer Design (Co-authored) 2015/10
Papers	A Fault Tolerant Response Analyzer with Self-Error-Correction Capability Proc. European Test Symp. 2015 2015/05
Papers	A practical approach for logic simplification based on fault acceptability for error tolerant application Proc. 20th IEEE European Test Symposium (Co-authored) 2015/05
Papers	Designing area-efficient controllers for multi-cycle transient fault tolerant systems Proc. 20th IEEE European Test Symposium (Co-authored) 2015/05
Papers	A controller design in high-level synthesis for long duration transient fault tolerance Digest of Papers 15th IEEE Workshop on RTL and High Level Testing (Co-authored) 2014/11
Papers	A scheduling algorithm in datapath synthesis for long duration transient fault tolerance Proc. 17th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems,pp.128-133 2014/10
Papers	Compact and Accurate Stochastic Circuits with Shared Random Number Sources Proc. IEEE International Conference on Computer Design,pp.361-366 (Co-authored) 2014/10
Papers	A System-Error-Rate-Oriented Approach to Test Generation for Effective Yield Maximization IEEE International Workshop on Reliability Aware System Design and Test (Co-authored) 2014/01
Papers	A Design of Error Correctable Response Analyzers for Reliable Built-in Self-test Digest of Papers 14th IEEE Workshop on RTL and High Level Testing (Co-authored) 2013/11
Papers	A Heuristic Algorithm for Operational Unit Binding to Synthesize Multi-Cycle Transient Fault Tolerant Datapaths Digest of Papers 14th IEEE Workshop on RTL and High Level Testing (Co-authored) 2013/11
Papers	A Transient Fault Tolerant Test Pattern Generator for On-line Built-in Self-test Proc. 22nd IEEE Asian Test Symp. (Co-authored) 2013/11
Papers	Utilizing register transfer level false paths for circuit optimization with a logic synthesis tool Proc. IEEE Asia Pacific Conference on Circuits and Systems,pp.615-618 (Co-authored) 2012/12
Papers	A Study on Error Correctable Test Pattern Generator for Reliable Built-in Self Test Dig. of Papers IEEE Workshop on RTL and High Level Testing (Co-authored) 2012/11
Papers	Exact and Heuristic Methods of Generating Compact Tests for Hold-time Violations Dig. of Papers IEEE Workshop on RTL and High Level Testing (Co-authored) 2012/11
Papers	Modeling Economics of LSI Design and Manufacturing for Test Design Selection Proc. Int. Conf. Computer Design (ICCD) 2013 (Co-authored) 2012/10
Papers	A Technique for SAT-based Test Generation through History of Reusing Solutions The 17th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2012) (Co-authored) 2012/03
Papers	Concurrent Testable Response Analyzer with Cyclic Code in Built-in Self-Test,pp.3-10 (Co-authored) 2012/03
Papers	Hybrid Test Application in Partial Skewed-load Scan Design IEICE Trans. Fundamentals E94-A (12),pp.2571-2578 (Co-authored) 2011/12
Papers	An approach to hardware SAT solvers for test generation based on instance similarity Dig. of Papers 12th IEEE Workshop on RTL and High Level Testing (Co-authored) 2011/11
Papers	Test Compression Based on Lossy Image Encoding IEEE Asian Test Symp. (ATS),pp.273-278 (Co-authored) 2011/11
Papers	High-Level Synthesis for Multi-Cycle Transient Fault Tolerant Datapaths Proc. IEEE Int. On-Line Testing Symp. (IOLTS),pp.13-18 (Co-authored) 2011/07
Papers	A Design of Response Analyzers with Self-Distinguishability in Built-in Self-Test Int. Symp. on Communications and Information Technologies (ISCIT),pp.732-735 (Co-authored) 2010/10
Papers	A Practical Threshold Test Generation for Error Tolerant Application IEICE Trans. Inf. & Syst. E93-D (10),pp.2776-2782 (Co-authored) 2010/10
Papers	An FPGA-Based Fail-soft System with Adaptive Reconfiguration 16th IEEE International On-Line Testing Symposium,pp.127-132 (Co-authored) 2010/07
Papers	Design and Optimization of Transparency-Based TAM for SoC Test IEICE Trans. Inf. & Syst. Vol. E93-D (6) (Co-authored) 2010/06
Papers	Hybrid Test Application in Hybrid Delay Scan Design IEEE Proc. ETS,pp.247 (Co-authored) 2010/05
Papers	A Fast Threshold Test Generation Algorithm Based on 5-Valued Logic IEEE Proc. DELTA,pp.345-349 (Co-authored) 2010/01
Papers	A Design of Concurrently Testable Response Analyzers in Built-in Self-Test Digest of Papers of 10th Workshop on RTL and High-Level Testing (WRTLT'09) (Co-authored) 2009/11
Papers	A Practical Approach to Threshold Test Generation for Error Tolerant Circuits IEEE Proc. ATS (Co-authored) 2009/11
Papers	Reliability and Performance Analysis of FPGA-Based Fault Tolerant System IEEE Proc. DFTS (Co-authored) 2009/10
Papers	A synthesis method to alleviate over-testing of delay faults based on RTL don't care path identification IEEE Proc. VLSI Test Symp. (Co-authored) 2009/05
Papers	Test Data Reduction by Test Point Insertion Based on Necessary Assignment Proc. European Test Symposium (Co-authored) 2009/05
Papers	Test Generation and DFT Based on Partial Thru Testability Proc. European Test Symposium (Co-authored) 2009/05
Papers	Fast False Path Identification Based on Functional Unsensitizability Using RTL Information Proc. the 14th Asia and South Pacific Design Automation Conference (ASP-DAC) (Co-authored) 2009/01
Papers	A Method for Test Data Reduction by Test Point Insertion Based on Necessary Assignment Digest of Papers of 9th Workshop on RTL and High-Level Testing(WRTLT'08),pp.105-110 (Co-authored) 2008/11
Papers	Reliability and Performance of FPGA-Based Fault Tolerant Systems Digest of Papers of 9th Workshop on RTL and High-Level Testing (WRTLT'08),pp.75-80 (Co-authored) 2008/11
Papers	A Self-Test of Dynamically Reconfigurable Processors with Test Frames Trans. Inf. & Syst. E91 (3),pp.756-762 (Co-authored) 2008/03
Papers	An Architecture of Embedded Decompressor with Reconfigurability for Test Compression Trans. Inf. & Syst. E91 (3),pp.713-719 (Co-authored) 2008/03
Papers	Test Compression / Decompression Based on JPEG VLC Algorithm Proc. Asian Test Symposium (Co-authored) 2007/10
Papers	A Variable-length Coding Adjustable for Compressed Test Application IEICE Trans. Inf. & Syst. (Co-authored) 2007/08
Papers	Optimal Contexts for the Self-Test of Coarse Grain Dynamically Reconfigurable Processors European Test Symp. (Co-authored) 2007/05
Papers	TAM Design and Optimization for Transparency-based SoC Test (Co-authored) 2007/05
Papers	A Reconfigurable Embedded Decompressor for Test Compression Proc. IEEE International Workshop on Electronic Design, Test & Applications,pp.301-306 (Co-authored) 2006/12
Papers	An Adaptive Decompressor for Test Application with Variable-Length Coding IPSJ Journal 47 (6),pp.1639-1647 (Co-authored) 2006
Papers	An Effective Design for Hierarchical Test Generation Based on Strong Testability Proc. IEEE Asian Test Symposium,pp.288-293 (Co-authored) 2005/12
Papers	A Test Generation for Compressible and Compact Test Sets IEICE Trans. D-I,pp.1021-1028 (Co-authored) 2005/06
Papers	A Huffman-based coding with efficient test application Proc. ASP-DAC,pp.75--78 (Co-authored) 2005/01
Papers	Huffman-Based Test Response Coding Trans. Inf. & Syst. E88-D (1),pp.158-161 (Co-authored) 2005/01
Papers	A Test Decompression Scheme for Variable-Length Coding Proc. Asian Test Symp.,pp.426-431 (Co-authored) 2004/11
Papers	Max-Testable Class of Sequential Circuits having Combinational Test Generation Complexity Proc. Asian Test Symp.,pp.342-347 (Co-authored) 2004/11
Papers	A Method of Test Generation for Acyclic Sequential Circuits Using Single Stuck-at Fault Combinational ATPG IEICE Trans. Fundamentals E86-A (12),pp.3072--3078 (Co-authored) 2003/12
Papers	Test Generation for Acyclic Sequential Circuits with Single Stuck-at Fault Combinational ATPG Proc. DATE03,pp.1180-1181 (Co-authored) 2003
Papers	Test Response Compression Based on Huffman Coding Proc. Asian Test symposium,pp.446-449 (Co-authored) 2003
Papers	Test generation for test compression based on statistical coding IEICE Trans. Inf. & Syst. E85-D (10),pp.1466-1473 (Co-authored) 2002/10
Papers	A scheduling method in high-level synthesis for acyclic partial scan design Proc. 11th IEEE Asian Test Symposium,pp.pp.128-133 (Co-authored) 2002
Papers	Generating small test sets for test compression / decomppression scheme using statistical coding Proc. 1st IEEE Int'l workshops on Electronic Design, Test and Applications,pp.pp.396-400 (Co-authored) 2002
Papers	Dynamic test compression using statistical coding Proc. 10th IEEE Asian Test Symp.,pp.143-148 (Co-authored) 2001
Papers	A partial scan design method for sequential circuits with hold registers IEICE Trans.,pp.981-990 (Co-authored) 2000/09
Papers	A binding method in high-level synthesis for testable datapaths based on acyclic partial scan design Trans. IEICE(D1),pp.282-292 (Co-authored) 2000/02
Papers	Test generation for acyclic sequential circuits with hold registers Proc. Int'l Conf. on Computer Aided Design,pp.550-556 (Co-authored) 2000
Papers	A high-level synthesis approach to partial scan design based on acyclic structure Proc. 8th IEEE Asian Test Symp.,pp.309-314 (Co-authored) 1999
Papers	Static and dynamic test sequence compaction methods for acyclic sequential circuits using a time expansion model Proc. 8th IEEE Asian Test Symp.,pp.192-199 (Co-authored) 1999
Papers	Testing for the programming circuit of SRAM-based FPGAs IEICE Trans. Inf. & Syst. E82-D (6),pp.1051-1057 (Co-authored) 1999
Papers	Test sequence compaction methods for acyclic sequential circuits using a time expansion model Trans. IEICE(D1),pp.869-878 (Co-authored) 1999
Papers	An optimal time expansion model based on combinational ATPG for RT level circuits Proc. IEEE the 7th Asian Test Symp.,pp.190-197 (Co-authored) 1998
Papers	Partial Scan Design Methods Based on Internally Balanced Structure Proc. Asia and South Pacific Design Automation Conf,pp.211-216 (Co-authored) 1998
Papers	Universal fault diagnosis for lookup table FPGAs IEEE Design & Test of Computers 15 (1),pp.39-44 (Co-authored) 1998
Papers	Partial Scan Design Methods Based on Internally Balanced Structure Trans. of IEICE(DI),pp.318-327 (Co-authored) 1998
Papers	On the complexity of universal fault diagnosis for Look-up table FPGAs Proc. Sixth IEEE Asian Test Symp,pp.276-281 (Co-authored) 1997
Papers	Sequential test generation based on circuit pseudo-transformation Proc. Sixth IEEE Asian Test Symp,pp.62-67 (Co-authored) 1997
Papers	Testing for the programming circuit of LUT-based FPGAs Proc. Sixth IEEE Asian Test Symp,pp.242-247 (Co-authored) 1997
Papers	An approach to sequential test generation by circuit pseudo-transformation Trans. of IPSJ,pp.1040-1049 (Co-authored) 1997
Papers	A test methodology for interconnect structures of LUT-based FPGAs Proc. Fifth IEEE Asian Test Symp.,pp.68-74 (Co-authored) 1996
Papers	An approach to the synthesis of synchronizable finite state machines with partial scan Proc. Fifth IEEE Asian Test Symp.,pp.130-135 (Co-authored) 1996
Papers	On the effect of scheduling in test generation IEICE Trans. on Information and Systems E79-D (8),pp.1190-1197 (Co-authored) 1996
Papers	Performance analysis of parallel test generation for combinational circuits IEICE Trans. on Information and Systems E79-D (9),pp.1257-1265 (Co-authored) 1996
Papers	A test methodology for configurable logic blocks of a look-up table FPGA IEICE Trans.,pp.1141-1150 (Co-authored) 1996
Papers	On the synthesis of synchronizable finite state machines with partial scan IEICE Trans.,pp.1046-1054 (Co-authored) 1996
Papers	A Scheduling Problem in Test Generation Proceedings IEEE VLSI Test Symposium,pp.344-349 (Co-authored) 1995
Papers	Optimal granularity and scheme of parallel test generation on the Client-Agent-Server model IEEE Transactions on Parallel and Distributed Systems 6 (7),pp.677-686 (Co-authored) 1995
Papers	Universal test complexity of field-programable gate arrays Proceedings of forth IEEE Asian Test Symposium,pp.259-265 (Co-authored) 1995
Papers	On the Performance Analysis of Parallel Processing for Test Generation Proceedings the 3rd IEEE Asian Test Symposium,pp.69-74 (Co-authored) 1994
Papers	Optimal Granularity of Parallel Test Generation on the Client-Agent-Server Model Transactions of Information Processing Society of Japan 35 (8),pp.1614-1623 (Co-authored) 1994
Papers	An Optimal Scheme of Parallel Processing for Test Generation in a Distributed System Proc. the Second Asian Test Symposium,pp.8-13 (Co-authored) 1993
Papers	Optimal Granularity of Test Generation in a Distributed System IEEE Transactions on Computer-Aided Design 9 (8),pp.885-892 (Co-authored) 1990
Papers	Analysis of Parallel Processing for Test Generation in a Distributed System Digest of Papers, the 1989 joint Symposium on Fault-Tolerant Computing,pp.128-133 (Co-authored) 1989
Papers	Optimal Granularity of Test Generation in a Distributed System Proceedings IEEE International Conference on Computer Aided Design,pp.158-161 (Co-authored) 1989