Faculty Information - Kojima Akira |

Kojima Akira

Department / Course

Hiroshima City University Graduate School Graduate School of Information Sciences Major in Computer and Network Engineering

Hiroshima City University Faculty of Information Sciences Department of Computer and Network Engineering

Job Research Associate

Book and thesis
Papers	Development of a Miniature Self-Driving Car Using SoC and NPU 2025 IEEE International Conference on Consumer Electronics (ICCE) (Sole-authored) 2025/01/11
Papers	Design of Miniature Automatic Driving Vehicle Controlled by Camera Image Processing 2024 IEEE International Conference on Consumer Electronics (ICCE) (Sole-authored) 2024/01/06
Papers	Implementation and Improvement of Autonomous Robot Car using SoC FPGA with DPU 2022 International Conference on Field-Programmable Technology (ICFPT) (Sole-authored) 2022/12/05
Papers	Autonomous Driving System implemented on Robot Car using SoC FPGA 2021 International Conference on Field-Programmable Technology (ICFPT) (Sole-authored) 2021/12/06
Papers	Design and Implementation of Autonomous Driving Robot Car Using SoC FPGA 2019 International Conference on Field-Programmable Technology (FPT),pp.441-444 (Co-authored) 2019/12/09
Papers	A Study of a Parallel Architecture for Accelerating Batch-Learning Self-Organizing Map by using Dedicated Hardware Proceedings of the 34th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2019),pp.104-107 (Co-authored) 2019/06/23
Papers	A Study on a Lane Keeping System using CNN for Online Learning of Steering Control from Real Time Images Proceedings of the 34th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2019),pp.499-502 (Co-authored) 2019/06/23
Papers	Implementation of Autonomous FPGA Robot Car Proc. 2019 International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (Co-authored) 2019/06/05
Papers	Development of an Autonomous Driving Robot Car using FPGA 2018 International Conference on Field-Programmable Technology (FPT),pp.411-414 (Co-authored) 2018/12/10
Papers	Consideration of Online Learning of Radial Basis Function Network for Engine Control and Acceleration using FPGA Proceedings of the 33rd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2018),pp.317-320 (Co-authored) 2018/07/04
Papers	Development of Experimental Robot and Laboratory Curriculum for Education of Embedded Technology and Network Technology,pp.373-374 (Co-authored) 2018/03/13
Papers	Consideration of Online Learning of Radial Basis Function Network for Engine Control and Acceleration using FPGA Proceedings of the 32nd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2017),pp.696-699 (Co-authored) 2017/07/02
Papers	Trax Player Implementation on FPGA using High Level Synthesis Tool 2016 International Conference on Field-Programmable Technology (FPT),pp.323-326 (Sole-authored) 2016/12/09
Papers	An Implementation of Trax player using programmable SoC 2015 International Conference on Field-Programmable Technology (FPT),pp.268-271 (Sole-authored) 2015/12/07
Papers	FPGA Implementation of Blokus Duo Player using Hardware/Software Co-Design 2014 International Conference on Field-Programmable Technology (FPT),pp.378-381 (Sole-authored) 2014/12/10
Papers	An implementation of Blokus Duo player on FPGA 2013 International Conference on Field-Programmable Technology (FPT),pp.506-509 (Sole-authored) 2013/12/09
Papers	Evaluation of Reconfigurable Computer System using Application of Parliamentary System,pp.37-42 (Co-authored) 2011/09/09
Papers	OS Functions for a Distributed FPGA Cluster System using Ethernet,pp.7-12 (Co-authored) 2010/11/30
Papers	Evaluation using Multiple Different Applications of OS for an FPGA-based Reconfigurable System,pp.75-80 (Co-authored) 2010/05/14
Papers	OS Functions for a Distributed FPGA Cluster System ITC-CSCC 2009 Proceeding,pp.565-568 (Co-authored) 2009/07
Papers	An Implementation of Operating System Functions for a Distributed FPGA Cluster System The Institute of Electronics, Information and Communication Engineers,pp.39-44 (Co-authored) 2008/09
Papers	Development and Implementation of OS Functions for a Computer System having FPGA Devices as Reconfigurable Resources Proceedings of the ITC-CSCC 2008,pp.141-144 (Co-authored) 2008/07
Papers	Implementation and Evaluation of OS Functions for a Computer System Having FPGA Devices,pp.95-100 (Co-authored) 2008/05
Papers	A Compiler Aimed Fast Compilation and High Quality Mapping for Dynamic Recongurable Processor based on VLIW model (Co-authored) 2007/11
Papers	An Implementation of Operating System Functions for a Reconfigurable System IEICE technical report,pp.13-18 (Co-authored) 2007/11
Papers	A Reconfigurable Processor 'PARS' and its Compiler Workshop on Innovative Archi-tecture for Future Generation High-Performance Processors and Systems(IWIA'07) (Co-authored) 2007/01
Papers	A Backend Compiler for a Coarse Grain Reconfigurable Architecture International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA), 2006 (Co-authored) 2006/01
Papers	PARS Architecture: A Reconfigurable Architecture with Generalized Execution Model --- Design and Implementation of its Prototype Processor IEICE Trans. on Information and Systems vol.E86-D (5),pp.830-840 (Co-authored) 2003/05
Papers	A Generalized Execution Model for Programming on Reconfigurable Architectures and an Architecture Supporting the Model Conference on Field Programmable Logic and Applications,pp.434-443 (Co-authored) 2002/08/16
Papers	Hash Parallel and Label Parallel Routing　for High Performance Multicast Router with Fine Grain QoS Control Proc. of IWS99,pp.13-16 (Co-authored) 1999/02
Papers	Estimation of Doacross Loops with Synchonization Costs and Experiments on Parallel Computers INFORMATION,pp.479-491 (Co-authored) 1999