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ツジ カツヒロ
Tsuji Katsuhiro
辻 勝弘
所属
広島市立大学大学院 情報科学研究科 システム工学専攻
広島市立大学 情報科学部 システム工学科
職種
助教
著書・論文歴
論文
Study on effective MOSFET channel length extracted from gate capacitance Japanese J. Appl. Phys. 57,016601-1-016601-7頁 (共著) 2018/01/01
論文
Study on Threshold Voltage Evaluated by Charge-Based Capacitance Measurement IEICE TRANSACTIONS on Electronics VOL.E99-C (NO.4),466-473頁 (共著) 2016/04
論文
Development of Test Structure for Variability Evaluation Using Charge-Based Capacitance Measurement IEICE TRANSACTIONS on Electronics VOL.E97-C (NO.11),1117-1123頁 (共著) 2014/11/01
論文
Reconsideration of Effective Channel Length for Metal-Oxide-Semiconductor Field Effect Transistor Japanese Journal of Applied Physics Vol. 53,064303 (共著) 2014/05
論文
Measurement of Channel Length Variability Proc. IEEE Workshop on Variability Modeling and Characterization at ICCAD (共著) 2013/11
論文
Effect of Channel Dopant Distribution on Effective Channel Length Extraction Jpn. J. Appl. Phys. 52 (064301) (共著) 2013/06
論文
Effective Channel Length Estimation Using Charge-Based Capacitance Measurement Proc. Int. Conf. on Microelectronic Test Structures,59-63頁 (共著) 2013/03
論文
Reconsideration of the Threshold Voltage Variability Estimated with Pair Transistor Cell Array Proc. Int. Conf. on Microelectronic Test Structures,108-111頁 (共著) 2013/03
論文
Effect of Channel Dopant Non-uniformity on Transconductance Variability Japanese Journal of Applied Physics 51 (094301) (共著) 2012/08
論文
Effect of channel dopant uniformity on MOSFET threshold voltage variability Solid-State Electronics 69,62-66頁 (共著) 2012/03
論文
Study on Device Matrix Array Structure for MOSFET gm Variability Evaluation Proc. Int. Conf. on Microelectronic Test Structures,73-76頁 (共著) 2012/03
論文
gm Variability Caused by Local Threshold-Voltage Fluctuation Proc. IEEE Workshop on Variability Modeling and Characterization at ICCAD,P1 (共著) 2011/11
論文
Effect of the Channel Dopant Non-Uniformity on VTH-Variation Proc. IEEE Workshop on Variability Modeling and Characterization at ICCAD,P4 (共著) 2010/11
論文
MOSFET-Array for Extracting Parameters Expressing SPICE-Parameter Variation Proc. Int. Conf. on Microelectronic Test Structures,76-79頁 (共著) 2010/03
論文
Measurement of MOSFET Drain Current Variation Under High Gate Voltage Solid State Electronics 53,314-319頁 (共著) 2009/03
論文
Extraction of effective LDMOSFET channel length and its application to the modeling Proc. Int. Conf. on Microelectronic Test Structures,81-84頁 (共著) 2000/03
論文
オフセットゲートMOSFETの回路モデル 電子情報通信学会論文誌 J-82-C-II,527-530頁 (共著) 1999/09
論文
Extraction of off-set region length for off-set gate MOSFETs Solid-State Electronics 43,97-102頁 (共著) 1999/01
論文
Measurement of channel length and off-set region length for off-set gate MOSFETs Proc. 27th European Solid State Device Research Conference,652-655頁 (共著) 1997/09
論文
Theoretical Study of Resonant Tunneling in Symmetrical Rectangular Triple-Barrier Structures with Deep Wells Materials Sciences & Engineering B 35,421-428頁 (共著) 1995/12
論文
Resonant Tunneling and Confining Phenomena in Symmetrical Rectangular Triple-Barrier Structures with C-type Double Wells Phys. Stat. Sol. (b) 188,679-688頁 (共著) 1995/04
論文
Resonant Tunneling and Confining Phenomena in Symmetrical Rectangular Triple-Barrier Structures with C-type Deep Wells Superlattices and Microstructures 17,35-39頁 (共著) 1995/01
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