Book and thesis
Papers
Study on effective MOSFET channel length extracted from gate capacitance Japanese J. Appl. Phys. 57,pp.016601-1-016601-7 (Co-authored) 2018/01/01
Papers
Study on Threshold Voltage Evaluated by Charge-Based Capacitance Measurement IEICE TRANSACTIONS on Electronics VOL.E99-C (NO.4),pp.466-473 (Co-authored) 2016/04
Papers
Development of Test Structure for Variability Evaluation Using Charge-Based Capacitance Measurement IEICE TRANSACTIONS on Electronics VOL.E97-C (NO.11),pp.1117-1123 (Co-authored) 2014/11/01
Papers
Reconsideration of Effective Channel Length for Metal-Oxide-Semiconductor Field Effect Transistor Japanese Journal of Applied Physics Vol. 53,pp.064303 (Co-authored) 2014/05
Papers
Measurement of Channel Length Variability Proc. IEEE Workshop on Variability Modeling and Characterization at ICCAD (Co-authored) 2013/11
Papers
Effect of Channel Dopant Distribution on Effective Channel Length Extraction Jpn. J. Appl. Phys. 52 (064301) (Co-authored) 2013/06
Papers
Effective Channel Length Estimation Using Charge-Based Capacitance Measurement Proc. Int. Conf. on Microelectronic Test Structures,pp.59-63 (Co-authored) 2013/03
Papers
Reconsideration of the Threshold Voltage Variability Estimated with Pair Transistor Cell Array Proc. Int. Conf. on Microelectronic Test Structures,pp.108-111 (Co-authored) 2013/03
Papers
Effect of Channel Dopant Non-uniformity on Transconductance Variability Japanese Journal of Applied Physics 51 (094301) (Co-authored) 2012/08
Papers
Effect of channel dopant uniformity on MOSFET threshold voltage variability Solid-State Electronics 69,pp.62-66 (Co-authored) 2012/03
Papers
Study on Device Matrix Array Structure for MOSFET gm Variability Evaluation Proc. Int. Conf. on Microelectronic Test Structures,pp.73-76 (Co-authored) 2012/03
Papers
gm Variability Caused by Local Threshold-Voltage Fluctuation Proc. IEEE Workshop on Variability Modeling and Characterization at ICCAD,pp.P1 (Co-authored) 2011/11
Papers
Effect of the Channel Dopant Non-Uniformity on VTH-Variation Proc. IEEE Workshop on Variability Modeling and Characterization at ICCAD,pp.P4 (Co-authored) 2010/11
Papers
MOSFET-Array for Extracting Parameters Expressing SPICE-Parameter Variation Proc. Int. Conf. on Microelectronic Test Structures,pp.76-79 (Co-authored) 2010/03
Papers
Measurement of MOSFET Drain Current Variation Under High Gate Voltage Solid State Electronics 53,pp.314-319 (Co-authored) 2009/03
Papers
Extraction of effective LDMOSFET channel length and its application to the modeling Proc. Int. Conf. on Microelectronic Test Structures,pp.81-84 (Co-authored) 2000/03
Papers
Extraction of off-set region length for off-set gate MOSFETs Solid-State Electronics 43,pp.97-102 (Co-authored) 1999/01
Papers
Measurement of channel length and off-set region length for off-set gate MOSFETs Proc. 27th European Solid State Device Research Conference,pp.652-655 (Co-authored) 1997/09
Papers
Theoretical Study of Resonant Tunneling in Symmetrical Rectangular Triple-Barrier Structures with Deep Wells Materials Sciences & Engineering B 35,pp.421-428 (Co-authored) 1995/12
Papers
Resonant Tunneling and Confining Phenomena in Symmetrical Rectangular Triple-Barrier Structures with C-type Double Wells Phys. Stat. Sol. (b) 188,pp.679-688 (Co-authored) 1995/04
Papers
Resonant Tunneling and Confining Phenomena in Symmetrical Rectangular Triple-Barrier Structures with C-type Deep Wells Superlattices and Microstructures 17,pp.35-39 (Co-authored) 1995/01