Book and thesis
Books
Reconfigurable Systems (Co-authored) 2005/08
Papers
Exploration of Acceleration of FPGA-based Linear Equation Solver using Approximate Division in Electronic Circuit Simulator,pp.93-98 (Co-authored) 2024/01/22
Papers
How to Support Programming with Algebraic Effects Effectively,pp.9-16 (Co-authored) 2024/01/06
Papers
Exploring Digital Tools to Revitalize Local Communities
Papers
Study of learning time for FPGA size of neural network that judges quality of place of logic elements in placement and routing of FPGA,pp.R23-26-11 (Co-authored) 2023/10/28
Papers
PROMELA to Erlang conversion tool for concurrent systems development,pp.R23-25-16 (Co-authored) 2023/10/28
Papers
Proposal of Breadth-First Search Accelerator using Parallel Hybrid Graph Traversal Algorithm,pp.R23-25-15 (Co-authored) 2023/10/28
Papers
Estimation of the number of memory accesses for the breadth-first search accelerator HyGTA,pp.129-129 (Co-authored) 2023/03/08
Papers
Initial Evaluation of FPGA Logic Element Placement Method Using Feature Extraction with Autoencoder,pp.13-18 (Co-authored) 2023/01/23
Papers
A Proposal for Acceleration of FPGA-based Linear Equation Solver using Speculative Execution System,pp.119-124 (Co-authored) 2023/01/23
Papers
Design of a Quadruple Precision Floating-Point Arithmetic Unit and its Evaluation by Conjugate Gradient Method,pp.138-142 (Co-authored) 2022/01/24
Papers
Development of specific cache memory for Hybrid Graph Traversal Algorithm,pp.117-122 (Co-authored) 2021/12/01
Papers
Rumpfr: A Fast and Memory Leak-free Rust Binding to the GNU MPFR Library Journal of Information Processing 29,pp.676-684 (Co-authored) 2021/10/15
Papers
Development of a simulator to explore the accelerator architecture for breadth-first search.,pp.8-13 (Co-authored) 2021/06/01
Papers
Rumpfr: a Fast and Memory Leak-Free Rust Binding to the MPFR Library,pp.1-10 (Co-authored) 2021/03/10
Papers
A Study on Coarse Grain Reconfigurable Architecture for Accelerating Mantissa Calculation of Multiple Precision Arithmetic,pp.42-42 (Co-authored) 2021/03/10
Papers
Acceleration of Atomic Image Reconstruction from X-ray Fluorescence Holograms on Multiple Platforms Proceedings of Materials Research Meeting (MRM2019),pp.A1-12-P41-A1-12-P41 (Co-authored) 2019/12/10
Papers
OSAIFU: A Source Code Factorizer on Android Studio 2019 IEEE International Conference on Software Maintenance and Evolution (ICSME),pp.422-425 (Co-authored) 2019/09/29
Papers
Efficient Searching for Essential API Member Sets based on Inclusion Relation Extraction International Journal of Networked and Distributed Computing 7 (4),pp.149-157 (Co-authored) 2019/09/24
Papers
SAIFU: Supporting Program Understanding by Automatic Indexing of Functionalities in Source Code International Journal of Networked and Distributed Computing 7 (4),pp.167-174 (Co-authored) 2019/09/24
Papers
A Study of Analysis Method of Overridden Event Listeners in Event-Driven Application for Extracting API Usage Pattern Information SIG Technical Reports,pp.1-7 (Co-authored) 2019/07/05
Papers
A Study of a Parallel Architecture for Accelerating Batch-Learning Self-Organizing Map by using Dedicated Hardware 2019 34th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC),pp.1-4 (Co-authored) 2019/06/23
Papers
A Study on a Lane Keeping System using CNN for Online Learning of Steering Control from Real Time Images 2019 34th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC),pp.1-4 (Co-authored) 2019/06/23
Papers
Extracting Inclusion Graphs of API Member Sets to Improve Searchability 2019 IEEE 17th International Conference on Software Engineering Research, Management and Applications (SERA),pp.53-59 (Co-authored) 2019/05/29
Papers
Supporting Program Understanding by Automatic Indexing of Functionalities in Source Code 2019 IEEE 17th International Conference on Software Engineering Research, Management and Applications (SERA),pp.13-18 (Co-authored) 2019/05/29
Papers
Easy-Going Development of Event-Driven Applications by Iterating a Search-Select-Superpose Loop Journal of Information Processing 27,pp.257-267 (Co-authored) 2019/03/15
Papers
Extracting Detailed Relations among API Member Sets by using Frequent Pattern Mining to Improve Searchability for Usable API Usage Patterns from Open-Source Repositories,pp.1-8 (Co-authored) 2019/02/28
Papers
Design and Evaluation of an Exercise-Style Class to Promote Active Learning ― A Case Study on the Introductory Class of Computer Systems ―,pp.1-10 (Co-authored) 2019/02/23
Papers
Resolving Ambiguous Types in Haskell by Checking Uniqueness of Type Variable Assignments under Type Class Constraints Journal of Information Processing 27,pp.87-94 (Co-authored) 2019/01/15
Papers
Traf: a Graphical Proof Tree Viewer Cooperating with Coq through Proof General Proc. of 16th Asian Symposium on Programming Languages and Systems (APLAS 2018) (LNCS 11275),pp.157-165 (Co-authored) 2018/12/02
Papers
A System for API Set Search for Supporting Application Program Development IEICE TRANSACTIONS on Information and Systems,pp.1176-1189 (Co-authored) 2018/08/01
Papers
FPGA Implementation of High-Performance SPICE Simulator for Small-Scale Electronic Circuits Proc. of the 33nd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2018),pp.317-320 (Co-authored) 2018/07/06
Papers
Trial Implementation of Large-Scale Graph Analysis with Breadth-First Search using FPGA with Multiport and Multibank Memory Proc. of the 33nd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2018),pp.321-324 (Co-authored) 2018/07/06
Papers
Supporting Program Understanding by Itemizing Summaries of Functionalities Extracted from Source Code,pp.1-8 (Co-authored) 2018/03/02
Papers
Design Algorithm for Reconfigurable Device MPLD/SePLD,pp.91-96 (Co-authored) 2017/08/31
Papers
A prototype design of reconfigurable device SePLD in 0.6um CMOS process Proc. of the 32nd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2017),pp.579-582 (Co-authored) 2017/07/05
Papers
Consideration of Online Learning of Radial Basis Function Network for Engine Control and Acceleration using FPGA Proc. of the 32nd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2017),pp.696-699 (Co-authored) 2017/07/05
Papers
Effective Indexing based on the TF-IDF Method with Selected Terms for Discovering Usages of APIs from Open Source Repositories Proc. of the 32nd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2017),pp.684-687 (Co-authored) 2017/07/05
Papers
Performance Improvement of an Exact Real Arithmetic Library, the IFN Library, by using the MPFI Library The 79th National Covenation of IPSJ,pp.319-320 (Co-authored) 2017/03/16
Papers
Performance Improvement of an Exact Real Arithmetic Library, the IFN Library, by using the MPFI Library The 79th National Covenation of IPSJ,pp.317-318 (Co-authored) 2017/03/16
Papers
Assembler environment utilizing pseudo-instructions for Pilaf a tiny microprocessor equipping eight machine-instructions 18th IEEE Hiroshima Section Student Symposium (HISS) A3-44,pp.1-4 (Co-authored) 2016/11/19
Papers
Analysis and evaluation of performance on parallel programming for FPGA and GPU by using OpenCL 18th IEEE Hiroshima Section Student Symposium (HISS) A4-54,pp.1-4 (Co-authored) 2016/11/19
Papers
A Study for Improving Processing Speed of SOM-based Placement Method for Fine-Grained Reconfigurable Device MPLD by List-type Data Structure 18th IEEE Hiroshima Section Student Symposium (HISS) A3-50,pp.1-4 (Co-authored) 2016/11/19
Papers
Consideration of Improving the Accuracy of the Cost Function of SA Method for MPLD Logic Cell Placement Problem 18th IEEE Hiroshima Section Student Symposium (HISS) B3-50,pp.1-4 (Co-authored) 2016/11/19
Papers
Consideration of selector based logic block SLB to configure a sequential circuit 18th IEEE Hiroshima Section Student Symposium (HISS) A3-49,pp.1-4 (Co-authored) 2016/11/19
Papers
Study on algorithm and architecture for the Center RADIUS-interval arithmetic for hardware 18th IEEE Hiroshima Section Student Symposium (HISS) B3-44,pp.1-4 (Co-authored) 2016/11/19
Papers
[Poster] Development of macro assembler for Microprocessor Pilaf designed for small IoT devices IEICE Tech. Rep.,CPSY2016-44,pp.11-12 (Co-authored) 2016/10/06
Papers
Proposal of small logic block SLB using selector FIT2016 The 15th science and technology forum,pp.15-22 (Co-authored) 2016/09/09
Papers
SOM-based placement method considering IO for fine-grain reconfigurable device MPLD IEICE Tech. Rep.,RECONF2016-30,pp.29-34 (Co-authored) 2016/08/29
Papers
Pilaf : Development ofultra-smallprocessor IP,pp.7-12 (Co-authored) 2015/10/08
Papers
Proposal of small reconfigurable device SePLD using selector,pp.53-58 (Co-authored) 2015/09/19
Papers
Design Consideration of a Secure Sensor Chip for Home Cancer Examination Proc. of the 30th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2015),pp.588-591 (Co-authored) 2015/07/01
Papers
Proposal of a small logic block for a reconfigurabl e device with flexibility on mapping of routing and logic cell Proc. of the 30th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2015),pp.511-514 (Co-authored) 2015/07/01
Papers
Consideration of a reconfigurable device MPLD constructed with MLUTs that equips a crossbar switch IEICE Tech. Rep.,RECONF2015-25,pp.135-245 (Co-authored) 2015/06/20
Papers
Consideration of the one-dimensional array processor suitable for a shock tube problem by FPGA IEICE Tech. Rep.,RECONF2015-9,pp.47-52 (Co-authored) 2015/06/19
Papers
Study of processor Pilaf for small-scale LSI Proc. of the 1st Education and Research Workshop of Electronic Devices, Circuits, Illuminations, and Systems,pp.3-3 (Co-authored) 2015/05/23
Papers
A Consideration on the Acceleration of Inlet-exhaust Pipes Simulation with GPGPU 16th IEEE Hiroshima Section Student Symposium (HISS) B-55,pp.1-5 (Co-authored) 2014/09/19
Papers
Discussion for speed up of three-dimensional space imaging using sound waves IEICE Tech. Rep.,RECONF2014-30,pp.75-80 (Co-authored) 2014/09/19
Papers
FPGA Implementation of a Compact Processor Yukiyama for Tiny SoC IEICE Tech. Rep.,RECONF2014-31,pp.81-86 (Co-authored) 2014/09/19
Papers
Study of accelerator connection using the peripheral bus of OpenMSP430 IEICE Tech. Rep.,RECONF2013-79,pp.137-142 (Co-authored) 2014/01/21
Papers
Architecture Evaluation Using The Place-and-Route Tool of a Reconstruction Device MPLD IEICE Tech. Rep.,RECONF2013-55,pp.87-92 (Co-authored) 2013/11/20
Papers
Soft-core microprocessor for small reconfigurable device IEICE Tech. Rep.,RECONF2013-46,pp.39-44 (Co-authored) 2013/11/20
Papers
Development of Somatometry Method using Kinect ---Stature Measurement and Scoliosis Examination---,pp.271-272 (Co-authored) 2013/10/19
Papers
Investigation of the area reduction by pass transistor logic in reconfigurable device MPLD IEICE Tech. Rep.,RECONF2013-28,pp.49-54 (Co-authored) 2013/09/11
Papers
Nonvolatile reconfigurable device development platform using a phase change material IEICE Tech. Rep.,RECONF2013-25,pp.31-36 (Co-authored) 2013/09/11
Papers
Proposal of a Dependable Fine-grained Reconfigurable Device with ECC Technology IEICE Tech. Rep.,RECONF2013-6,pp.31-36 (Co-authored) 2013/05/13
Papers
Evaluation of Reconfigurable Computer System using Application of Parliamentary System IEICE Tech. Rep.,RECONF2012-61,pp.1-6 (Co-authored) 2013/01/16
Papers
Performance Evaluation of RC-OS or Multiple FPGA Clusters IEICE Tech. Rep.,RECONF2012-57,pp.57-62 (Co-authored) 2012/11/27
Papers
Using Reconfigurable Architecture as a Universal Computing Engine NII Shonan Meeting Report No.2012-11 The NII Shonan Configurable Computing Workshop,pp.5-6 (Sole-authored) 2012/11/12
Papers
Evaluation of Reconfigurable Computer System using Application of Parliamentary System IEICE Tech. Rep.,RECONF2012-9,pp.49-54 (Co-authored) 2012/05/29
Papers
Net-based Move in SA-based Placement for a Switch-Block-Free Reconfigurable Device In Proc. The 17th Workshop on Synthesis And System Integration of Mixed Information technologies,pp.239-240 (Co-authored) 2012/03/08
Papers
A Physical Design Method for a New Memory-based Reconfigurable Architecture without Switch Blocks IEICE Trans. on Information and Systems,pp.11pages (Co-authored) 2012/02
Papers
EDA Environment for Evaluating a New Switch-Block- Free Reconfigurable Architecture Proc. of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig),pp.448-454 (Co-authored) 2011/11/30
Papers
Design Consideration for Reconfigurable Processor DS-HIE Proc. of the 2011 International SoC Design Conference,pp.187-190 (Co-authored) 2011/11/18
Papers
Evaluation of Reconfigurable Computer System using Application of Parliamentary System IEICE Tech. Rep.,RECONF2011-28,pp.37-42 (Co-authored) 2011/09/26
Papers
Evaluation of Reconfigurable Computer System using Application of Parliamentary System IEICE Tech. Rep.,RECONF2011-36,pp.81-86 (Co-authored) 2011/09/26
Papers
Feasibility study of Nonvolatile Reconfigurable Device by using a Standerd CMOS logic process IEICE Tech. Rep.,RECONF2011-23,pp.7-12 (Co-authored) 2011/09/26
Papers
Memory Array Based PLD Architecture for High-Density Logic Mapping – Implementation of First Demo Chip – Proc. of the IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XIV),poster1,pp.1page (Co-authored) 2011/04/20
Papers
Development and Performance Evaluation of Multiple Precision Floating Point Accelerator HP-DSFP IEICE TRANSACTIONS on Information and Systems,pp.334-343 (Co-authored) 2011/01/01
Papers
OS Functions for a Distributed FPGA Cluster System using Ethernet IEICE Tech. Rep.,RECONF2010-40,pp.7-12 (Co-authored) 2010/11/23
Papers
Design and Implementation of a Layout Tool for the MPLD Architecture IEICE Tech. Rep.,RECONF2010-27,pp.55-60 (Co-authored) 2010/09/17
Papers
A Consideration of Reconfigurable Processor for RSA Cryptography IEICE Tech. Rep. RECONF2010-22,pp.25-30 (Co-authored) 2010/09/16
Papers
Evaluation of Multiple-Precision Floating-Point Accelerator HP-DSFP through Applications IEICE Tech. Rep., RECONF2010-25,pp.43-48 (Co-authored) 2010/09/16
Papers
An SA-based Placement and Routing Method Considering Cell Congestion for MPLDs IEICE Tech. Rep.,RECONF2010-26,pp.49-54 (Co-authored) 2010/09/16
Papers
Development and Evaluation of Accelerator of Finite Element Method by using a C-Based Design Tool,pp.pp. 39–44 (Co-authored) 2010/09/02
Papers
Digit-Serial Floating Point Unit for High Precision Scientific Computation Engine IEICE Tech. Rep.,RECONF2010-6,pp.31-36 (Co-authored) 2010/05/14
Papers
Evaluation using Multiple Different Applications of OS for an FPGA-based Reconfigurable System IEICE Tech. Rep., RECONF2010-14,pp.75-80 (Co-authored) 2010/05/14
Papers
Comparison of Bit Serial Computation with Bit Parallel Computation for Reconfigurable Processor In Proceedings of the 6th International Workshop on Applied Reconfigurable Computing (ARC 2010),pp.388–393 (Co-authored) 2010/03/18
Papers
Evaluation using Applications for RC-OS which supports Reconfigurable Computer System IEICE Tech. Rep., RECONF2009-57,pp.19-24 (Co-authored) 2010/01/27
Papers
Performance Evaluation for Reconfigurable Part of Reconfigurable Processor based on Bit Serial Operation IEICE TRANSACTIONS on Information and Systems,pp.2089-2104 (Co-authored) 2009/12/01
Papers
A study of an Implementation Method of a Mathematical Function in Reconfigurable Accelerator with High-Precision Floating Point Arithmetic IEICE Tech. Rep.,RECONF2009-39,pp.119-124 (Co-authored) 2009/09/18
Papers
High-density Implementation for Reconfigurable Device MPLD IEICE Tech. Rep.,RECONF2009-35,pp.97-102 (Co-authored) 2009/09/18
Papers
Consideration of Data Transfer Unit in Reconfigurable Processor DS-HIE IEICE Tech. Rep.,RECONF2009-29,pp.61-66 (Co-authored) 2009/09/18
Papers
A Proposal for a Method to Generate Optimized Dataflow for Reconfigurable Processor DS-HIE Based on Bit Serial Operation IEICE Tech. Rep.,RECONF2009-28,pp.55-60 (Co-authored) 2009/09/17
Papers
OS Functions for a Distributed FPGA Cluster System Proceedings of the ITC-CSCC 2009,pp.565-568 (Co-authored) 2009/07
Papers
Performance Evaluation of Reconfigurable Processor Hy-DiSC based on MeP Hardware Extension IEICE Tech. Rep., RECONF2009-1,pp.1-6 (Co-authored) 2009/05/14
Papers
Evaluation of Compact High-Throughput Reconfigurable Architecture Based on Bit-Serial Computation International Conference on Field-Programmable Technology,pp.273-276 (Co-authored) 2008/12
Papers
The Proposal of the MPLD Architecture for High Performance Computing (Special Invited Talk) IEICE Tech. Rep., CPSY2008-31,pp.13-18 (Co-authored) 2008/10/31
Papers
EXPLORING COMPACT DESIGN ON HIGH THROUGHPUT COARSE GRAINED RECONFIGURABLE ARCHITECTURES Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL),pp.543-546 (Co-authored) 2008/09
Papers
Development and Evaluation of Raytracing Acceleration Engine with Bit Serial Arithmetic Units Proceedings of the 23rd International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC2008),pp.237-240 (Co-authored) 2008/07
Papers
Development and Implementation of OS Functions for a Computer System having FPGA Devices as Reconfigurable Resources Proceedings of the 23rd International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC2008),pp.141-144 (Co-authored) 2008/07
Papers
Development of Compiler which Supports High-level Programming Language for Dynamic Reconfigurable Architecture DS-HIE Proceedings of the 23rd International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC2008),pp.405-408 (Co-authored) 2008/07
Papers
Development of Heterogenous Multi-core Processor "Hy-DiSC" with Dynamic Reconfigurable Processor Proceedings of the 23rd International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC2008),pp.145-148 (Co-authored) 2008/07
Papers
Low Cost PLD with High Speed Partial Reconfiguration Proceedings of the 23rd International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC2008),pp.557-560 (Co-authored) 2008/07
Papers
Evaluation of Low Energy and High Performance Processor using Variable Stages Pipeline Technique IET Computers & Digital Techniques -- May 2008 -- 2 (3),pp.230-238 (Co-authored) 2008/05
Papers
A PLD Architacture for High Performance Computing Proceedings of the International Workshop on Innovative Archi-tecture for Future Generation High-Performance Processors and Systems(IWIA'08),pp.3ページ (Co-authored) 2008/01
Papers
A PLD Architacture for High Performance Computing Proc. International Workshop on Innovative Archi-tecture for Future Generation High-Performance Processors and Systems (IWIA'08),pp.1-3 (Co-authored) 2008/01
Papers
4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words IEICE Trans Electron 2007 E90-C (11),pp.2157-2160 (Co-authored) 2007/11
Papers
Development of Operating System Managing Multiple FPGA Resources,pp.(d) 情報 (Co-authored) 2007/11
Papers
Development of DS-HIE Architecture Proceedings of the 2007 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2007) 1,pp.47-48 (Co-authored) 2007/07
Papers
A Reconfigurable Processor 'PARS' and its Compiler International Workshop on Innovative Archi-tecture for Future Generation High-Performance Processors and Systems(IWIA'07),pp.91-100 (Co-authored) 2007/01
Papers
Multi-Bank Register File for Increased Performance of Highly-Parallel Processors Extended Abstracts of the Fifth Hiroshima International Workshop on Nanoelectronics for Tera-Bit Information Processing,pp.130-133 (Co-authored) 2007/01
Papers
Unified data/instruction cache with hierarchical multi-port architecture and hidden precharge pipeline 2006 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS2006),pp.1299-1302 (Co-authored) 2006/12
Papers
Access Queues for Multi-Bank Register Files Enabling Enhanced Performance of Highly Parallel Processors Proc. of the 2006 IEEE Region 10 Conference (TENCON 2006),pp.Session CA2.4 (4pages) (Co-authored) 2006/11/14
Papers
Multi-bank register file for increased performance ofhighly-parallel processors Proceedings of the 32nd European Solid-State Circuits Conference(ESSCIRC2006),pp.154-157 (Co-authored) 2006/09
Papers
A Design and Evaluation of Low Energy Processor by Variable Stages Pipeline Technique Transactions of IPS Japan: Computer systems ACS14,pp.231-242 (Co-authored) 2006/05
Papers
Evaluation of Bank based Multi-port Memory Architecture with Blocking Network Systems & Computers in Japan 37 (2),pp.22-33 (Co-authored) 2006/02
Papers
Superscalar Processor with Multi-Bank Register File Post Proc. 8th International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05),pp.3-12 (Co-authored) 2005/11
Papers
Chip Size and Performance Evaluations of Shared Cache for On-chip Multiprocessor Systems & Computers in Japan 36 (9),pp.79-95 (Co-authored) 2005/09
Papers
A Design of Prototype Low Energy Processor by Variable Stages Pipeline Technique Proceedings of the 2005 International Technical Conference on Circuits/Systems, Computers and Communications,pp.561-562 (Co-authored) 2005/07
Papers
Evaluation of the n Bit-Serial Arithmetic Units in Consideration of Trade-off between Area and Performance Proceedings of the 2005 International Technical Conference on Circuits/Systems, Computers and Communications,pp.943-944 (Co-authored) 2005/07
Papers
Design of Superscalar Processor with Multi-Bank Register File Proc. of 2005 IEEE International Symposium on Circuits and Systems (ISCAS2005),pp.3507-3510 (Co-authored) 2005/05
Papers
Evaluation of a Bank Based Multi-port Memory Architecture with Blocking Network The IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,pp.498-510 (Co-authored) 2005/04
Papers
Prototype educational FPGA board with graphical display FPGA/PLD Design Conference 2005,pp.71-77 (Co-authored) 2005/01
Papers
Multi-bank based Switch Architecture with Flexible Scheduled Buffering of Packets Extended Abstracts of the Third Hiroshima International Workshop on Nanoelectronics for Tera-Bit Information Processing,pp.52-53 (Co-authored) 2004/12
Papers
Unified Data/Instruction Cache with Bank-Based Multi-Port Architecture Extended Abstracts of the Third Hiroshima International Workshop on Nanoelectronics for Tera-Bit Information Processing,pp.50-51 (Co-authored) 2004/12
Papers
Highly Efficient Switch Architecture Based on Banked Memory with Multiple Ports Proceedings of the Workshop on Synthesis And System Intergration of Mixed Information Technologies (SASIMI 2004),pp.491-498 (Co-authored) 2004/10
Papers
A Coarse-Grained Reconfigurable Architecture Supporting Flexible Execution Proceedings of IEEE HPCAsia2004 the 7th International Conference on High Performance Computing and Grid in Asia Pacific Region,pp.448-449 (Co-authored) 2004/07
Papers
Fundamental training that should be done before DA: Experiment of Fundamental Information Engineering IPSJ Proc. Design Automation Sympo.,pp.31-36 (Co-authored) 2004/07
Papers
Low Energy Consumption by a Variable Stages Pipeline Technique Proceedings of the 2004 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2004),pp.1-4 (Co-authored) 2004/07
Papers
Low Power Bank-based Multi-port SRAM Design due to Bank Standby Mode Proceedings of the 47th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS2004),pp.569-572 (Co-authored) 2004/07
Papers
Proposition and Evaluation of a Bank based Multi-port Memory with Blocking Network Proceedings of the 2004 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2004),pp.1-4 (Co-authored) 2004/07
Papers
Chip Size and Performance Evaluations of Shared Cache for On-chip Multiprocessor The IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,pp.350-363 (Co-authored) 2004/03
Papers
Development and the Future Directions of RRAM Function & Materials,pp.30-39 (Sole-authored) 2004/02
Papers
Distributed against centralised crossbar function for realising bank-based multiport memories Electronics Letters,pp.101-102 (Co-authored) 2004/02
Papers
Compact 12-port multi-bank register file test-chip in 0.35um CMOS for highly parallel processors Proceedings of the Asia South Pacific Design Automation Conference 2004 (ASP-DAC2004),pp.551-552 (Co-authored) 2004/01
Papers
Verification and evaluation that uses general-purpose system environment MPE FPGA/PLD Design Conference 2004,pp.113-120 (Co-authored) 2004/01
Papers
Distributed-crossbar architecture for area-efficient combined data/instruction caches with multiple ports Electronics Letters,pp.160-162 (Co-authored) 2004
Papers
A Coarse-Grained Reconfigurable Architecture with Low Cost Configuration Data Compression Mechanism IEEE International Conference on Field-Programmable Technology (FPT'03),pp.311-314 (Co-authored) 2003/12
Papers
A hierarchical 512-Kbit SRAM with 8 read/write ports in 130nm CMOS Extended Abstracts of the 2003 International Conference on Solid State Devices and Materials (SSDM2003),pp.150-151 (Co-authored) 2003/09
Papers
A Novel Hierarchical Multi-port Cache The 29th European Solid-State Circuits Conference (ESSCIRC2003),pp.405-408 (Co-authored) 2003/09
Papers
Bank-type multiport register file for highly parallel processors Extended Abstracts of the 2003 International Conference on Solid State Devices and Materials (SSDM2003),pp.400-401 (Co-authored) 2003/09
Papers
Combined Data/Instruction Cache with Bank-Based Multi-Port Architecture Extended Abstracts of the 2003 International Conference on Solid State Devices and Materials (SSDM2003),pp.152-153 (Co-authored) 2003/09
Papers
PARS Architecture: A Reconfigurable Architecture with Generalized Execution Model --- Design and Implementation of Its Prototype Processor Transaction Information & System,pp.830-840 (Co-authored) 2003/05
Papers
A High-Speed and Low Power Hierarchical Multi-port Cache Proceedings of COOL Chips VI - An International Symposium on Low-Power and High-Speed Chips,pp.76-76 (Co-authored) 2003/04
Papers
High Access Bandwidth Multi-Port-Cache Design with Compact Hierarchical 1-Port-Bank Structure Proceedings of the Workshop on Synthesis And System Intergration of Mixed Information Technologies (SASIMI 2003),pp.394-400 (Co-authored) 2003/04
Papers
Optimized Bank-Based Multi-Port Memories through a Hierarchical Multi-Bank Structure Proceedings of the Workshop on Synthesis And System Intergration of Mixed Information Technologies (SASIMI 2003),pp.323-333 (Co-authored) 2003/04
Papers
FPGA/PLD towards System on Chip Platform DESIGN WAVE MAGAZINE Feb.,pp.14-17 (Sole-authored) 2003/01
Papers
A Generalized Execution Model for Programming on Reconfigurable Architectures and an Architecture Supporting the Model Proceedings of the 12th International Conference on Field Programmable Logic and Application,pp.434-443 (Co-authored) 2002/09
Papers
Implementation of the Reconfigurable Processor with Ability of Every-cycle Reconfiguration and Execution Proc. of the IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips V) Vol.1,pp.162-162 (Co-authored) 2002/04
Papers
Detail Design of Evaluation Circut Board for Operation Verification for Multiprocessors Proc. FPGA/PLD Design Conference 2002,pp.85-92 (Co-authored) 2002/01
Papers
Scheduling Support Hardware for Multiprocessor System and Its Evaluations The IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,pp.1515-1531 (Co-authored) 2001/11
Papers
Performance Improvements of Thakore's Algorithm with Speculative Execution Technique and Dynamic Task Scheduling, Infomatica An International Journal of Computing and Informatics,pp.33-38 (Co-authored) 2000/03
Papers
Prototype Microprocessor LSI with Scheduling Support Hardware for Operating System on Multiprocessor System Proceedings of the Asia and South Pacific Design Automation Conference 2000(ASP-DAC 2000),pp.29-30 (Co-authored) 2000/01
Papers
Microprocessor LSI with Scheduling Support Hardware for Operating System on Multiprocessor System Proceedings of the 6-th Asia Pacific Conference on cHip Design Languages (APCHDL'99),pp.67-72 (Co-authored) 1999/10
Papers
Performance Improvement of Thakore's Algorithm in Parallel Object-Oriented Databases Proceedings of the 1999 International Symposium on Database, Web and Cooperative Systems (DWACOS'99),pp.123-130 (Co-authored) 1999/08
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Applying Thakove's Algorithm in Parallel Object-Oriented Databases with Multi-transaction Environment IPSJ Joint Symposium on Parallel Processing 1998,pp.319-326 (Co-authored) 1998/06
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Expansion of Video Database by Introducing Speculative Execution Technique in Parallel Environments Proceedings of 1997 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing,pp.256-259 (Co-authored) 1997/08
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Introduction of FPGA Integrated DRAM and Memory Systems THE FIFTH JAPANESE FPGA/PLD DESIGN CONFERENCE,pp.223-231 (Co-authored) 1997/06
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Improving Query Time of a Object-Oriented Database by Introducing Speclative Execution Technique in Parallel Environments Transactions of IPS Japan,pp.2274-2285 (Co-authored) 1997/06
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Speculating Queries : Another way for Parallel Processing on Databases IEICE The 8-th Database Engineering Work Shop 1997,pp.263-268 (Co-authored) 1997/03
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Hyperscalar Processor Architecture ---Principle of Operations and Performance Evaluation--- Transactions of IPS Japan,pp.1964-1975 (Co-authored) 1995/08
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Hyperscalar Processor Architecture and the Preliminary Performance Evaluation Engineering Sciences Reports,pp.29-40 (Co-authored) 1995/06
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Hyperscalar Processor Architecture ---Desiga and Performance Evalution of the Prototype Processor--- Joint Symposium on Parallel Processing 1994,pp.9-16 (Co-authored) 1994/05
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A Micro-vectorprocessor Architecture --- Performance Modeling and Benchmarking --- Proceedings of ACM-SIGARCH 1993 International Conference on SUPERCOMPUTING,pp.308-317 (Co-authored) 1993/07
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A Vector-Processor Prototype Based on MSFV (Multithreaded Streaming/FIFO Vector ) Architecture ---Evaluation of MSFV Architecture--- Transaction of IPS Japan,pp.658-668 (Co-authored) 1993/04
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A Vector Microprocessor Architecture International Symposium on Logic Synthesis and Microprocessor Architectures (ISKIT'92),pp.47-54 (Co-authored) 1992/08
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Benchmarking a Vector-Processor Prototype Based on Multithreaded Streaming/FIFO Vector (MSFV) Architecture Proceedings of ACM-SIGARCH 1992 International Conference on SUPERCOMPUTING,pp.272-281 (Co-authored) 1992/07
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[Jyunpu]: A MSF Type Prototype Vector Processor ---Evaluation of MSFV Architecture--- IPSJ Joint Symposium on Parallel Processing 1992,pp.359-366 (Co-authored) 1992/05
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A SINGLE-CHIP VECTOR-PROCESSOR PROTOTYPE BASED ON MULTITHREADED STREAMING/FIFO VECTOR (MSFV) ARCHITECTURE Proceedings of the International Symposium on Supercomputing,pp.77-86 (Co-authored) 1991/07
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A Vector Processor Based on Streaming/FIFO Architecture ---Evaluation for Implementing Streaming/FIFO Architecture and Virtual Pipeline--- Transaction of IPS Japan,pp.828-837 (Co-authored) 1991/07
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[Jyunpu]: A Prototype Vector Processor Based on Streaming/FIFO Architecture ---Evaluation of Macro Operation, Vector-Scalar Cooperative processing and Vector Instruction Terminating Operation--- Joint Symposium on Parallel Processing 1991,pp.101-108 (Co-authored) 1991/05
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The Architecture and Evaluation of Vector Processor based on Streamming FIFO method Joint Symposium on Parallel Processing 1990,pp.201-208 (Co-authored) 1990/05
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Low-level Parallel Processing Algorithms for the SIMP Processor Prototype Transaction of IPS Japan,pp.1603-1611 (Co-authored) 1989/12