Faculty Information - Iwagaki Tsuyoshi |

（Last updated : 2024-08-23 16:54:58）

Iwagaki Tsuyoshi

Department / Course Hiroshima City University Graduate School Graduate School of Information Sciences Major in Computer and Network Engineering

Hiroshima City University Faculty of Information Sciences Department of Computer and Network Engineering

Job Research Associate

E-Mail Address

Home Page
http://www.cd.info.hiroshima-cu.ac.jp/~iwagaki/

Business career
2011/08/01 ～	Research Associate Hiroshima City University Faculty of Information Sciences Department of Computer and Network Engineering
2011/08/01 ～	Research Associate Hiroshima City University Graduate School Graduate School of Information Sciences Major in Computer and Network Engineering
2010/10 ～ 2011/02	Honorary Fellow, University of Wisconsin-Madison

Academic background
2002/04～2004/09	Doctoral Program (2nd Semester) Graduate School of Information Science Nara Institute of Science and Technology Finished
2000/04～2002/03	Doctoral Program (1st Semester) Graduate School of Information Science Nara Institute of Science and Technology Finished
1996/04～2000/03	Department of Electronics Engineering Faculty of Engineering Osaka Institute of Technology Graduated

Present specialized field
Computer system keyword(Design and Test of Digital Systems, Dependable Computing, Asynchronous Circuits, High Level Synthesis, Test Generation, Design for Testability)

Book and thesis
Books	Broadside transition test generation for partial scan circuits through stuck-at test generation (Co-authored) 2007
Papers	A Design of Fully Stochastic Computing Neurons Focused on the Gain of Sigmoid Functions,pp.552-561 (Co-authored) 2021/07
Papers	Transient Fault Tolerant State Assignment for Stochastic Computing Based on Linear Finite State Machines IEICE Trans. Fundamentals E103-A (12),pp.1464-1471 (Co-authored) 2020/12
Papers	State encoding with stochastic numbers for transient fault tolerant linear finite state machines Proc. 32nd IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT '19),pp.1-6 (Co-authored) 2019/10
Papers	An empirical approach to RTL scan path design focusing on structural interpretation in logic synthesis Proc. 3rd IEEE International Test Conference in Asia (ITC-Asia '19),pp.55-60 (Co-authored) 2019/09
Display All（56）

Academic conference presentation
2017/11	Stochastic number generation with internal signals of peripheral logic circuits (電子情報通信学会VLD研究会)
2017/02	Impact of operational unit binding on aging-induced degradation in high-level synthesis for asynchronous systems (電子情報通信学会DC研究会)
2014/01	A system-error-rate-oriented approach to test generation for effective yield maximization (5th IEEE International Workshop on Reliability Aware System Design and Test (RASDAT '14))

Winning science prize
2012/11	11th IEEE Workshop on RTL and High Level Testing Best Paper Award
2004/11	4th IEEE Workshop on RTL and High Level Testing Best Paper Award

Activity in society
2023 ～	34th IEEE Asian Test Symposium (ATS 2025) / 9th IEEE International Test Conference in Asia (ITC-Asia 2025) Publicity Chair
2022 ～ 2023	7th IEEE International Test Conference in Asia (ITC-Asia 2023) Publicity Chair
2021 ～ 2022	IEICE Transactions A (Special Section on Circuits and Systems) Guest Associate Editor
2020 ～ 2020	35th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC) TPC member
2018 ～ 2021	30th IEEE Asian Test Symposium (ATS 2021) Publicity Chair
Display All（9）